公开(公告)号：US20240193339A1

公开(公告)日：2024-06-13

申请号：US18532496

申请日：2023-12-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jordan Timothy Davis ,  Woojin Seo ,  Chanhee Jeon

IPC分类号： G06F30/392 ,  G06F30/327 ,  G06F30/394

CPC分类号： G06F30/392 ,  G06F30/327 ,  G06F30/394 ,  G06F2115/06

摘要： In an example method of analyzing an electrostatic discharge (ESD) network, input data characterizing a semiconductor device is received. The semiconductor device includes an input/output (I/O) pad, an ESD protection circuit, and at least one functional circuit. A common resistance of the ESD protection circuit is calculated based on the input data and using a plurality of resistances and at least one predetermined equation. The plurality of resistances are associated with the I/O pad, the ESD protection circuit, and the at least one functional circuit. A network analysis is performed on the semiconductor device by excluding the common resistance.

公开(公告)号：US11681853B2

公开(公告)日：2023-06-20

申请号：US17692767

申请日：2022-03-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Sheng-Hsiung Chen ,  Wen-Hao Chen ,  Hung-Chih Ou ,  Chun-Yao Ku ,  Shao-Huan Wang

IPC分类号： G06F30/30 ,  G06F30/398 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396 ,  G06F115/06 ,  G06F119/06 ,  G06F119/12 ,  G06F30/392

CPC分类号： G06F30/398 ,  G06F30/337 ,  G06F30/3315 ,  G06F30/396 ,  G06F30/392 ,  G06F2115/06 ,  G06F2119/06 ,  G06F2119/12

摘要： A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

公开(公告)号：US11651127B2

公开(公告)日：2023-05-16

申请号：US17399523

申请日：2021-08-11

申请人： Xilinx, Inc.

发明人： Stephen Andrew Neuendorffer ,  Jianyi Cheng

IPC分类号： G06F30/323 ,  G06F30/343 ,  G06F115/06

CPC分类号： G06F30/323 ,  G06F30/343 ,  G06F2115/06

摘要： Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.

公开(公告)号：US11663382B1

公开(公告)日：2023-05-30

申请号：US16140320

申请日：2018-09-24

申请人： ARCHITECTURE TECHNOLOGY CORPORATION

发明人： Joseph Cascioli

IPC分类号： G06F21/57 ,  G06F16/58 ,  G06F30/33 ,  G06F21/76 ,  G06F30/39 ,  G06F30/333 ,  G06F115/06 ,  G06F119/18

CPC分类号： G06F30/33 ,  G06F21/577 ,  G06F21/76 ,  G06F30/39 ,  G06F30/333 ,  G06F2115/06 ,  G06F2119/18

摘要： Disclosed herein is application specific integrated circuit (ASIC) redesign for security and analysis testing tool, which includes hardware description language code with on-chip security circuitry for detecting and mitigating hardware Trojan horses (HTHs) in an ASIC chip. The testing tool is used between a design stage of the ASIC chip and a synthesis phase of production of the ASIC chip to add test circuitry to the ASIC chip in order to facilitate testing and protecting of the ASIC chip from the HTHs long after production. The test circuitry facilitates search for HTHs, HTH triggering events, and changes made to the ASIC if the HTH has been activated.

公开(公告)号：US20230144599A1

公开(公告)日：2023-05-11

申请号：US18094190

申请日：2023-01-06

申请人： CHRONOS TECH LLC

发明人： Stefano GIACONI ,  Giacomo RINALDI ,  Matheus TREVISAN MOREIRA ,  Matthew PRYOR ,  David FONG

IPC分类号： G06F30/34 ,  H04L47/10 ,  H04L12/40 ,  G06F13/42 ,  G06F30/30 ,  G06F30/35 ,  G06F30/394

CPC分类号： G06F30/34 ,  G06F13/4295 ,  G06F30/30 ,  G06F30/35 ,  G06F30/394 ,  H04L12/40006 ,  H04L47/10 ,  G06F2115/06

摘要： Systems and methods for providing Chronos Channel interconnects in an ASIC are provided. Chronos Channels rely on a reduced set of timing assumptions and are robust against delay variations. Chronos Channels transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic. Chronos Channels are insensitive to all wire and gate delay variations, but for those belonging to a few specific forking logic paths called isochronic forks. Chronos Channels use temporal compression in internal paths to reduce the overheads of QDI logic and efficiently transmit data. Chronos Channels are defined by a combination of a DI code, a temporal compression ratio and hardware.

公开(公告)号：US20240338511A1

公开(公告)日：2024-10-10

申请号：US18746888

申请日：2024-06-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Sheng-Hsiung CHEN ,  Wen-Hao CHEN ,  Hung-Chih OU ,  Chun-Yao KU ,  Shao-Huan WANG

IPC分类号： G06F30/398 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/392 ,  G06F30/396 ,  G06F115/06 ,  G06F119/06 ,  G06F119/12

CPC分类号： G06F30/398 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396 ,  G06F30/392 ,  G06F2115/06 ,  G06F2119/06 ,  G06F2119/12

摘要： A multi-bit flip-flop includes a first flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The first flip-flop includes a first set pin configured to receive a first set signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together. The first flip-flop and the second flip-flop are configured to share at least a first clock pin.

公开(公告)号：US20230334219A1

公开(公告)日：2023-10-19

申请号：US18337245

申请日：2023-06-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Sheng-Hsiung CHEN ,  Wen-Hao CHEN ,  Hung-Chih OU ,  Chun-Yao KU ,  Shao-Huan WANG

IPC分类号： G06F30/398 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396

CPC分类号： G06F30/398 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396 ,  G06F2115/06

摘要： A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

公开(公告)号：US12124783B2

公开(公告)日：2024-10-22

申请号：US17636785

申请日：2020-08-20

申请人： Google LLC

发明人： Michial Allen Gunter ,  Reiner Pope ,  Pavel Krajcevski ,  Clifford Biffle

IPC分类号： G06F30/347 ,  G06F115/06 ,  H04L49/253

CPC分类号： G06F30/347 ,  H04L49/253 ,  G06F2115/06

摘要： A method of configuring an integrated circuit including multiple hardware tiles, includes: establishing a data forwarding path through the multiple hardware tiles by configuring each hardware tile, except for a last hardware tile, of the multiple hardware tiles to be in a data forwarding state, in which configuring each hardware tile, except for the last hardware tile, to be in a forwarding state includes installing a respective forwarding state counter specifying a corresponding predefined length of time that the hardware tile is in the data forwarding state; supplying, along the data forwarding path, each hardware tile of the plurality of hardware tiles with a respective program data packet comprising program data for the hardware tile; and installing, for each hardware tile of the multiple hardware tiles, the respective program data.

公开(公告)号：US12014131B2

公开(公告)日：2024-06-18

申请号：US18337245

申请日：2023-06-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Sheng-Hsiung Chen ,  Wen-Hao Chen ,  Hung-Chih Ou ,  Chun-Yao Ku ,  Shao-Huan Wang

IPC分类号： G06F30/30 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396 ,  G06F30/398 ,  G06F30/392 ,  G06F115/06 ,  G06F119/06 ,  G06F119/12

CPC分类号： G06F30/398 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396 ,  G06F30/392 ,  G06F2115/06 ,  G06F2119/06 ,  G06F2119/12

摘要： A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

公开(公告)号：US11941336B2

公开(公告)日：2024-03-26

申请号：US17523525

申请日：2021-11-10

申请人： OPPSTAR TECHNOLOGY SDN BHD

发明人： Kim Pin Tan ,  Hun Wah Cheah

IPC分类号： G06F30/347 ,  G06F115/06

CPC分类号： G06F30/347 ,  G06F2115/06

摘要： Circuit devices include a first chip that includes functional blocks. A second chip has routing circuitry that provides configurable signal communications between functional blocks of the first chip and configuration memory that controls the routing circuitry and that further controls operation of the functional blocks of the first chip.