公开(公告)号：US20180151490A1

公开(公告)日：2018-05-31

申请号：US15792911

申请日：2017-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin YIM ,  Jongmin BAEK ,  Deokyoung JUNG ,  Kyuhee HAN ,  Byunghee KIM ,  Jiyoung KIM ,  Naein LEE ,  Sangshin JANG

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.

公开(公告)号：US20240421162A1

公开(公告)日：2024-12-19

申请号：US18529716

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minchul AHN ,  Yeonggil KIM ,  Sungbin PARK ,  Deokyoung JUNG

IPC: H01L27/12

Abstract: An integrated circuit device includes a backside insulating structure including an etch stop pattern, gate lines arranged over the backside insulating structure and each overlapping the etch stop pattern in a vertical direction, source/drain regions respectively arranged one-by-one between the gate lines, and a backside via contact passing through the etch stop pattern in the vertical direction and connected to a first source/drain region selected from the source/drain regions, wherein the backside via contact includes a stepped portion, which is apart from a first vertical level in the vertical direction by as much as a first distance and has a change in the width of the backside via contact in a horizontal direction at a second vertical level that is adjacent to the etch stop pattern, the first vertical level being closest to the plurality of gate lines in the backside insulating structure.

公开(公告)号：US20170200675A1

公开(公告)日：2017-07-13

申请号：US15403480

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokyoung JUNG ,  Kwangjin MOON ,  Byung Lyul PARK ,  Jin Ho AN

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76826 ,  H01L21/76886 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2225/06544 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor substrate including a first surface and a second surface opposite the first surface, a front insulating layer on the first surface of the semiconductor substrate, a back insulating layer on the second surface of the semiconductor substrate, a through via structure extending through the back insulating layer, the semiconductor substrate, and the front insulating layer, a via insulating layer on a side surface of the through via structure, and a contact structure extending through the front insulating layer. The through via structure may include a first region and a second region disposed on the first region. The second region may include a first doping element, and the first region may be substantially free of the first doping element.