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公开(公告)号:US20230072375A1
公开(公告)日:2023-03-09
申请号:US17984874
申请日:2022-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sanghoon AHN , Woojin LEE , Kyuhee HAN
IPC: H01L21/768 , H01L23/522 , H01L23/532
Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.
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2.
公开(公告)号:US20190096636A1
公开(公告)日:2019-03-28
申请号:US15940621
申请日:2018-03-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sang Ki NAM , Sung Yong LIM , Beomjin YOO , Jongwoo SUN , Kyuhee HAN , Kwangyoub HEO , Je-Woo HAN
IPC: H01J37/32
Abstract: A plasma processing apparatus includes a chamber including a space for processing a substrate, a substrate stage supporting the substrate within the chamber and including a lower electrode, an upper electrode within the chamber facing the lower electrode, a first power supply including a sinusoidal wave power source configured to apply a sinusoidal wave power to the lower electrode to form plasma within the chamber, and a second power supply configured to apply a nonsinusoidal wave power to the upper electrode to generate an electron beam.
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3.
公开(公告)号:US20210151300A1
公开(公告)日:2021-05-20
申请号:US17021166
申请日:2020-09-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jieun JUNG , Siqing LU , Soonam PARK , Kyuhee HAN
IPC: H01J37/32
Abstract: A substrate processing apparatus and a method of manufacturing a semiconductor device, the apparatus including a plasma region in which plasma is generated; a processing region in which a substrate is processable; a shower head including a first channel and a second channel, the first channel being a passage through which the plasma flows between the plasma region and the processing region and the second channel being a passage through which a process gas is supplied to the processing region, the first channel and the second channel being separated from each other; a substrate support supporting the substrate in the processing region; and a cooler configured to supply a cooling fluid to a cooling channel of the substrate support.
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公开(公告)号:US20210125856A1
公开(公告)日:2021-04-29
申请号:US16872955
申请日:2020-05-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sanghoon AHN , Woojin LEE , Kyuhee HAN
IPC: H01L21/768 , H01L23/522 , H01L23/532
Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.
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公开(公告)号:US20210110997A1
公开(公告)日:2021-04-15
申请号:US16850252
申请日:2020-04-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dongkyu SHIN , Sangki NAM , Soonam PARK , Akira KOSHIISHI , Kyuhee HAN
IPC: H01J37/32 , H01J37/063 , H01L21/67 , H01L21/683 , H01L21/3065
Abstract: An electron beam generator, a plasma processing apparatus, and a plasma processing method, the electron beam generator including a side insulator configured to surround the substrate support, the side insulator having an electron beam chamber therein; a first electrode embedded in the side insulator and adjacent to a first side wall of the electron beam chamber; a second electrode on a second side wall of the electron beam chamber; and a guide in an outlet of the electron beam chamber, the guide including slits through which electron beams generated in the electron beam chamber are transmittable into the process chamber.
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公开(公告)号:US20230187178A1
公开(公告)日:2023-06-15
申请号:US17993055
申请日:2022-11-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Youngil KANG , Byeongsang KIM , Jongmu KIM , Yongbeom PARK , Dougyong SUNG , Yunjae LEE , Seugkyu LIM , Kyuhee HAN
IPC: H01J37/32
CPC classification number: H01J37/3244 , H01J2237/335 , H01J37/32724
Abstract: A substrate processing apparatus includes: a process chamber; a substrate support structure disposed at a lower portion of the process chamber and configured to accommodate a substrate; and a gas supply module disposed at an upper portion of the process chamber and supplying a process gas to the substrate, wherein the gas supply module includes a showerhead that includes: a first showerhead body including a plurality of injection ports configured to transfer gas transferred from a gas inlet into the process chamber; and a coating layer covering the first showerhead body and including aluminum fluoride, wherein the first showerhead body includes a metal matrix composite (MMC).
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公开(公告)号:US20230175113A1
公开(公告)日:2023-06-08
申请号:US17849914
申请日:2022-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaesuk KIM , Sangwook PARK , Gukrok YUN , Kyuhee HAN
CPC classification number: C23C14/351 , H01J37/3405 , H01J37/32651 , H01J37/345 , H01J37/3417 , H01J2237/332
Abstract: A physical vapor deposition (PVD) apparatus includes: a vacuum chamber; a pedestal arranged in the vacuum chamber and configured to support a substrate; a target arranged on the vacuum chamber and including a deposition material; a shield arranged on an inner sidewall of the vacuum chamber toprotect the vacuum chamber from the deposition material; a target power supply applying a target voltage to the target to generate plasma in the vacuum chamber; and a magnet configured to induce the plasma to the target; and a magnetic field formation line connected with the target power supply, wherein the magnetic field formation line surrounds the shield symmetrically with respect to a center of the shield to form a magnetic field in the vacuum chamber.
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8.
公开(公告)号:US20190279846A1
公开(公告)日:2019-09-12
申请号:US16421433
申请日:2019-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yeongkwang LEE , Sunggil KANG , Sang Ki NAM , Kwangyoub HEO , Kyuhee HAN
IPC: H01J37/32
Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.
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公开(公告)号:US20180151490A1
公开(公告)日:2018-05-31
申请号:US15792911
申请日:2017-10-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Taejin YIM , Jongmin BAEK , Deokyoung JUNG , Kyuhee HAN , Byunghee KIM , Jiyoung KIM , Naein LEE , Sangshin JANG
IPC: H01L23/522 , H01L23/532 , H01L21/768
CPC classification number: H01L23/5222 , H01L21/76802 , H01L21/7682 , H01L21/76831 , H01L21/76843 , H01L23/5226 , H01L23/5228 , H01L23/53238 , H01L23/53295
Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.
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