公开(公告)号：US20240413246A1

公开(公告)日：2024-12-12

申请号：US18809745

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20240297221A1

公开(公告)日：2024-09-05

申请号：US18405389

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd. ,  University-Industry Cooperation Group Of Kyung Hee University

Inventor： Changseok LEE ,  Seunghyun LEE ,  Minsu SEOL ,  Dohee KIM ,  Junseong BAE ,  Hyeyoon RYU ,  Sangwon KIM ,  Kyung-Eun BYUN

IPC: H01L29/16 ,  H01L29/167 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/1606 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/778

Abstract: A transistor structure may include a semiconductor structure may include a substrate; a source electrode and a drain electrode spaced apart from each other on the substrate; a channel layer connected to the source electrode and the drain electrode; a gate insulating layer on the channel layer; and a gate electrode on the gate insulating layer. The channel layer may include a two-dimensional semiconductor material. The source electrode and the drain electrode each may include a graphene layer and a metal layer. The graphene layer may be formed by as-growing on the substrate. The graphene layer and the metal layer may be side by side in a vertical direction with respect to a surface of the substrate.

公开(公告)号：US20220069134A1

公开(公告)日：2022-03-03

申请号：US17206229

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Seunghun LEE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; channel layers vertically spaced apart on the active region; a gate structure extending in a second direction and intersecting the active region, the gate structure surrounding the channel layers; a source/drain region on the active region in contact with the channel layers; and a contact plug connected to the source/drain region, wherein the source/drain region includes a first epitaxial layer on side surfaces of the channel layers and including a first impurity; a second epitaxial layer on the first epitaxial layer and including the first impurity and a second impurity; and a third epitaxial layer on the second epitaxial layer and including the first impurity, and in a horizontal sectional view, the second epitaxial layer includes a peripheral portion having a thickness in the first direction that increases along the second direction.

公开(公告)号：US20230268441A1

公开(公告)日：2023-08-24

申请号：US18307279

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/41791 ,  H01L29/6681 ,  H01L21/823431 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20220238666A1

公开(公告)日：2022-07-28

申请号：US17404078

申请日：2021-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee KIM ,  Gyeom KIM ,  Jinbum KIM ,  Jaemun KIM ,  Seunghun LEE

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088

Abstract: An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction.

公开(公告)号：US20240105842A1

公开(公告)日：2024-03-28

申请号：US18456934

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghwan JANG ,  Dohee KIM ,  Pyung MOON ,  Sunguk JANG ,  Mina SEOL

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L29/40

CPC classification number: H01L29/7827 ,  H01L21/02532 ,  H01L21/308 ,  H01L29/401

Abstract: In a method of manufacturing a semiconductor device, a first selective epitaxial growth (SEG) process is performed on a substrate to form a first channel. A first etching process is performed to form a first recess through the first channel and an upper portion of the substrate. A sidewall of the first channel exposed by the first recess is slanted with respect to an upper surface of the substrate. A second SEG process is performed to form a second channel on a surface of the substrate and the sidewall of the first channel exposed by the first recess. A gate structure is formed to fill the first recess. An impurity region is formed at an upper portion of the substrate adjacent to the gate structure.

公开(公告)号：US20230137340A1

公开(公告)日：2023-05-04

申请号：US17858150

申请日：2022-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohee KIM ,  Sunguk JANG ,  Sahwan HONG ,  Kongsoo LEE

IPC: H01L27/108

Abstract: A pattern formation method includes forming a first capping layer on a substrate, forming a recess that penetrates the first capping layer and an upper portion of the substrate, such that a non-penetrated portion of the first capping layer constitutes a first capping pattern, forming a second capping pattern that covers an inner sidewall of the recess, and forming a stack structure in the recess, such that the stack structure includes first stack patterns and second stack patterns that are alternately stacked, and the second capping pattern is between the substrate and a lateral surface of the stack structure.

公开(公告)号：US20220005946A1

公开(公告)日：2022-01-06

申请号：US17192301

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.