公开(公告)号：US20170139769A1

公开(公告)日：2017-05-18

申请号：US14941051

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Evgeny BLAICHMAN ,  Moshe TWITTO ,  Avner DOR ,  Elona EREZ ,  Jun Jin KONG ,  Shay LANDIS ,  Yaron SHANY ,  Yoav SHERESHEVSKI

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/098 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/455

Abstract: A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

公开(公告)号：US20160054930A1

公开(公告)日：2016-02-25

申请号：US14463129

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Avner DOR ,  Elona EREZ ,  Jun Jin KONG

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0641 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1453 ,  G06F17/30159

Abstract: At least one example embodiment discloses a method of determining a similarity in a nonvolatile memory. The method includes obtaining first data and second data units, the first data unit divided into a first plurality of non-overlapping chunks of data and the second data unit divided into a second plurality of non-overlapping chunks of data, determining a first plurality of values associated with the first plurality of chunks and a second plurality of values associated with the second plurality of chunks and determining a similarity between the first data unit and the second data unit based on whether any of the first plurality of values equals any of the second plurality of values.

Abstract translation: 至少一个示例性实施例公开了一种确定非易失性存储器中的相似性的方法。 该方法包括：获取第一数据和第二数据单元，将第一数据单元划分为第一多个非重叠的数据块，以及将第二数据单元划分成第二多个非重叠的数据块， 与第一多个块相关联的值和与第二多个块相关联的第二多个值，并且基于第一多个值中的任一个是否等于第二多个块中的任何一个来确定第一数据单元和第二数据单元之间的相似度 多个值。

公开(公告)号：US20160117256A1

公开(公告)日：2016-04-28

申请号：US14523159

申请日：2014-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Avner DOR ,  Elona EREZ ,  Shay LANDIS ,  Jun Jin KONG

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.

Abstract translation: 至少一个示例性实施例公开了一种控制包括多个块的非易失性存储器件的方法，每个块包括多个物理页。 该方法包括分别接收与第一多个逻辑地址相关联的多个逻辑页面，并根据第一多个逻辑页面的逻辑地址的升序将多个逻辑页面写入多个物理地址。

公开(公告)号：US20190065392A1

公开(公告)日：2019-02-28

申请号：US15684252

申请日：2017-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Elona EREZ ,  Avner DOR ,  Moshe TWITTO ,  Jun Jin KONG

IPC: G06F12/1009 ,  G06F12/02

Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.