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    Method of equalizing bit error rates of memory device
    1.
    发明授权
    Method of equalizing bit error rates of memory device 有权

    公开(公告)号：US11126497B2

    公开(公告)日：2021-09-21

    申请号：US16358884

    申请日：2019-03-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eun-chu Oh ,  Moo-sung Kim ,  Young-sik Kim ,  Yong-jun Lee ,  Jeong-ho Lee

    IPC: G06F11/10 ,  G11C29/52 ,  G06F11/07 ,  G11C13/00

    Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

    METHOD OF EQUALIZING BIT ERROR RATES OF MEMORY DEVICE
    4.
    发明申请
    METHOD OF EQUALIZING BIT ERROR RATES OF MEMORY DEVICE 有权

    公开(公告)号：US20220004455A1

    公开(公告)日：2022-01-06

    申请号：US17478597

    申请日：2021-09-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eun-chu Oh ,  Moo-sung Kim ,  Young-sik Kim ,  Yong-jun Lee ,  Jeong-ho Lee

    IPC: G06F11/10 ,  G06F11/07 ,  G11C29/52 ,  G11C13/00

    Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

    Memory controller and operating method thereof
    5.
    发明授权
    Memory controller and operating method thereof 有权

    公开(公告)号：US10990523B2

    公开(公告)日：2021-04-27

    申请号：US16445005

    申请日：2019-06-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeong-ho Lee ,  Young-sik Kim ,  Eun-chu Oh ,  Young-kwang Yoo ,  Young-geun Lee

    IPC: G06F12/06 ,  G06F1/32 ,  G06F3/06 ,  G06F12/02

    Abstract: A memory controller configured to control a memory device including a plurality of banks. The memory controller may determine whether a number of write commands enqueued in a command queue of the memory controller exceeds a reference value, calculate a level of write power to be consumed by the memory device in response to at least some of the write commands from among the enqueued write commands when the number of enqueued write commands exceeds the reference value, and schedule, based on the calculated level of write power, interleaving commands executing an interleaving operation of the memory device, from among the enqueued write commands.

    Memory, memory system, and error checking and correcting method for memory
    6.
    发明授权
    Memory, memory system, and error checking and correcting method for memory 有权
    内存，内存系统和内存的错误检查和纠正方法

    公开(公告)号：US09136872B2

    公开(公告)日：2015-09-15

    申请号：US13648421

    申请日：2012-10-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eun-chu Oh ,  Jae-hong Kim ,  Jun-jin Kong

    IPC: G06F11/00 ,  H03M13/05 ,  H03M13/35 ,  H03M13/37 ,  H03M13/11

    CPC classification number: H03M13/05 ,  H03M13/1102 ,  H03M13/356 ,  H03M13/3707

    Abstract: A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method.

    Abstract translation: 存储器系统包括错误检查和校正（ECC）引擎，其被配置为根据第一方法执行临时存储在第一存储器阵列中的数据的错误校验和校正以及从第一存储器阵列读出的数据，并执行错误校验和校正 根据第二方法从第一存储器阵列读出并从第二存储器阵列读出的数据中存储在第二存储器阵列中的数据，其中响应于至少具有至少一个控制信号的控制信号选择第一方法和第二方法 第一种逻辑级别，第二种方法检查和纠正以比较第一种方法更高速率发生的数据错误。

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