公开(公告)号：US20200159618A1

公开(公告)日：2020-05-21

申请号：US16405427

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu OH ,  Young-jin Cho ,  Young-geun Lee

IPC: G06F11/10 ,  G11C29/52 ,  G11C13/00 ,  G11C11/16

Abstract: A memory controller is provided. The memory controller includes an error correction code (ECC) circuit configured to correct an error of a read codeword provided from a memory device, the ECC circuit including: a codeword combination generator configured to receive a first read codeword including a plurality of first read codeword bit values that are read from a first region of the memory device, generate a change codeword by changing values of one or more of the plurality of first read codeword bit values, and provide a codeword combination including the change codeword; and an ECC decoder including a plurality of ECC engines, wherein the ECC decoder is configured to perform ECC decoding in parallel on a plurality of codewords included in the codeword combination.

公开(公告)号：US10990523B2

公开(公告)日：2021-04-27

申请号：US16445005

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-ho Lee ,  Young-sik Kim ,  Eun-chu Oh ,  Young-kwang Yoo ,  Young-geun Lee

IPC: G06F12/06 ,  G06F1/32 ,  G06F3/06 ,  G06F12/02

Abstract: A memory controller configured to control a memory device including a plurality of banks. The memory controller may determine whether a number of write commands enqueued in a command queue of the memory controller exceeds a reference value, calculate a level of write power to be consumed by the memory device in response to at least some of the write commands from among the enqueued write commands when the number of enqueued write commands exceeds the reference value, and schedule, based on the calculated level of write power, interleaving commands executing an interleaving operation of the memory device, from among the enqueued write commands.

公开(公告)号：US11307918B2

公开(公告)日：2022-04-19

申请号：US16594400

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun chu Oh ,  Young-Sik Kim ,  Hee-hyun Nam ,  Young-geun Lee ,  Young-jin Cho

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/34 ,  G11C11/409 ,  G11C11/408 ,  G06F13/16 ,  G11C29/52 ,  G11C11/16 ,  G11C13/00 ,  G11C29/04

Abstract: A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.

公开(公告)号：US10777282B2

公开(公告)日：2020-09-15

申请号：US16531787

申请日：2019-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Young-geun Lee

IPC: G11C16/34 ,  G11C16/26 ,  G11C29/42 ,  G06F11/22 ,  G06F13/16 ,  G11C29/04

Abstract: A memory controller to control a memory device includes an Error Checking and Correcting (ECC) engine to perform error detection on data read from the memory device and a data operation manager. The data operation manager is to control a first rewrite operation of the memory device on selected memory cells to compensate for a drift in a distribution of the selected memory cells, based on a result of a test read operation of the memory device on test cells, determine a distribution adjustment degree based on a result of a normal read operation, as an ECC decoding operation corresponding to the normal read operation of the memory device is successfully performed by using the ECC engine, and control a second rewrite operation of the memory device based on the determined distribution adjustment degree.

公开(公告)号：US20200159602A1

公开(公告)日：2020-05-21

申请号：US16594400

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun chu Oh ,  Young-Sik Kim ,  Hee-hyun Nam ,  Young-geun Lee ,  Young-jin Cho

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/34 ,  G06F13/16 ,  G11C11/409 ,  G11C11/408

Abstract: A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.