公开(公告)号：US08940557B2

公开(公告)日：2015-01-27

申请号：US13921415

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-won Kim ,  Jong-youn Kim ,  Eun-kyoung Choi ,  Sang-uk Han ,  Ji-seok Hong

IPC: H01L21/66 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Abstract translation: 制造晶片级封装的方法包括制备包括多个第一半导体芯片的晶片，将多个第二半导体芯片安装在晶片上，将晶片设置在下模具上，并且设置上模以围绕边缘 在晶片的上表面上分配模制构件，并且通过使用柱塞对模制构件加压，以便制造其中暴露多个第二半导体芯片中的每一个的顶表面的晶片级封装。

公开(公告)号：US20130344627A1

公开(公告)日：2013-12-26

申请号：US13921415

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd

Inventor： Sang-won Kim ,  Jong-youn Kim ,  Eun-kyoung Choi ,  Sang-uk Han ,  Ji-seok Hong

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Abstract translation: 制造晶片级封装的方法包括制备包括多个第一半导体芯片的晶片，将多个第二半导体芯片安装在晶片上，将晶片设置在下模具上，并且设置上模以围绕边缘 在晶片的上表面上分配模制构件，并且通过使用柱塞对模制构件加压，以便制造其中暴露多个第二半导体芯片中的每一个的顶表面的晶片级封装。