公开(公告)号：US08901727B2

公开(公告)日：2014-12-02

申请号：US13774209

申请日：2013-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myun-sung Kang ,  Jung-min Ko ,  Sang-sick Park ,  Won-keun Kim ,  Ji-seok Hong

IPC: H01L25/10 ,  H01L23/28 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip. A first underfill layer is positioned between the second semiconductor chip and the first semiconductor chip; a second underfill layer is positioned between the third semiconductor chip and the second semiconductor chip, and a third underfill layer is positioned between the fourth semiconductor chip and the third semiconductor chip. In some embodiments, the second underfill layer comprises a material that is different than the first and third underfill layers.

Abstract translation: 半导体封装包括第一半导体芯片，第一半导体芯片上的第二半导体芯片，第二半导体芯片上的第三半导体芯片和第三半导体芯片上的第四半导体芯片。 第一底部填充层位于第二半导体芯片和第一半导体芯片之间; 第二底部填充层位于第三半导体芯片和第二半导体芯片之间，第三底层填充层位于第四半导体芯片和第三半导体芯片之间。 在一些实施例中，第二底部填充层包括不同于第一和第三底部填充层的材料。

公开(公告)号：US10910346B2

公开(公告)日：2021-02-02

申请号：US16445861

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-seok Hong ,  Ji-hoon Kim

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.

公开(公告)号：US11329024B2

公开(公告)日：2022-05-10

申请号：US16942084

申请日：2020-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-seok Hong ,  Jin-woo Park

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

公开(公告)号：US08940557B2

公开(公告)日：2015-01-27

申请号：US13921415

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-won Kim ,  Jong-youn Kim ,  Eun-kyoung Choi ,  Sang-uk Han ,  Ji-seok Hong

IPC: H01L21/66 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Abstract translation: 制造晶片级封装的方法包括制备包括多个第一半导体芯片的晶片，将多个第二半导体芯片安装在晶片上，将晶片设置在下模具上，并且设置上模以围绕边缘 在晶片的上表面上分配模制构件，并且通过使用柱塞对模制构件加压，以便制造其中暴露多个第二半导体芯片中的每一个的顶表面的晶片级封装。

公开(公告)号：US20130344627A1

公开(公告)日：2013-12-26

申请号：US13921415

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd

Inventor： Sang-won Kim ,  Jong-youn Kim ,  Eun-kyoung Choi ,  Sang-uk Han ,  Ji-seok Hong

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Abstract translation: 制造晶片级封装的方法包括制备包括多个第一半导体芯片的晶片，将多个第二半导体芯片安装在晶片上，将晶片设置在下模具上，并且设置上模以围绕边缘 在晶片的上表面上分配模制构件，并且通过使用柱塞对模制构件加压，以便制造其中暴露多个第二半导体芯片中的每一个的顶表面的晶片级封装。

公开(公告)号：US11984425B2

公开(公告)日：2024-05-14

申请号：US17569657

申请日：2022-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-seok Hong ,  Jin-woo Park

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06586

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

公开(公告)号：US10790264B2

公开(公告)日：2020-09-29

申请号：US16366044

申请日：2019-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-seok Hong ,  Jin-woo Park

IPC: H01L25/16 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.