公开(公告)号：US11462464B2

公开(公告)日：2022-10-04

申请号：US17110542

申请日：2020-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L25/065 ,  H01L21/48

Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.

公开(公告)号：US11710701B2

公开(公告)日：2023-07-25

申请号：US17743805

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005

Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

公开(公告)号：US08940557B2

公开(公告)日：2015-01-27

申请号：US13921415

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-won Kim ,  Jong-youn Kim ,  Eun-kyoung Choi ,  Sang-uk Han ,  Ji-seok Hong

IPC: H01L21/66 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Abstract translation: 制造晶片级封装的方法包括制备包括多个第一半导体芯片的晶片，将多个第二半导体芯片安装在晶片上，将晶片设置在下模具上，并且设置上模以围绕边缘 在晶片的上表面上分配模制构件，并且通过使用柱塞对模制构件加压，以便制造其中暴露多个第二半导体芯片中的每一个的顶表面的晶片级封装。

公开(公告)号：US20130344627A1

公开(公告)日：2013-12-26

申请号：US13921415

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd

Inventor： Sang-won Kim ,  Jong-youn Kim ,  Eun-kyoung Choi ,  Sang-uk Han ,  Ji-seok Hong

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Abstract translation: 制造晶片级封装的方法包括制备包括多个第一半导体芯片的晶片，将多个第二半导体芯片安装在晶片上，将晶片设置在下模具上，并且设置上模以围绕边缘 在晶片的上表面上分配模制构件，并且通过使用柱塞对模制构件加压，以便制造其中暴露多个第二半导体芯片中的每一个的顶表面的晶片级封装。

公开(公告)号：US12170249B2

公开(公告)日：2024-12-17

申请号：US18332494

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

公开(公告)号：US11355440B2

公开(公告)日：2022-06-07

申请号：US17100171

申请日：2020-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

公开(公告)号：US11101231B2

公开(公告)日：2021-08-24

申请号：US16819851

申请日：2020-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-youn Kim ,  Seok-hyun Lee ,  Youn-ji Min ,  Kyoung-lim Suk ,  Seok-won Lee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/683 ,  H01L25/065 ,  H01L23/498

Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.

公开(公告)号：US20200043840A1

公开(公告)日：2020-02-06

申请号：US16299307

申请日：2019-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538

Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.