公开(公告)号：US20250079425A1

公开(公告)日：2025-03-06

申请号：US18820834

申请日：2024-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsil Kang

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip structure on the first substrate, a second semiconductor chip structure on the first substrate and spaced apart from the first semiconductor chip structure in a first horizontal direction, an underfill material layer filling a space between the first semiconductor chip, the second semiconductor chip structure and the first substrate, and an outermost layer at least partially covering the underfill material layer exposed between the first semiconductor chip, the second semiconductor chip and the first substrate.

公开(公告)号：US11948851B2

公开(公告)日：2024-04-02

申请号：US17332471

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunjae Kim ,  Eunsil Kang ,  Daehyun Kim ,  Sunkyoung Seo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L21/561 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0557 ,  H01L2224/06519 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161

Abstract: A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.