公开(公告)号：US20240128319A1

公开(公告)日：2024-04-18

申请号：US18322234

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunwoo KIM ,  Wandon KIM ,  Jaeseoung PARK ,  Hyunbae LEE ,  Jeonghyuk YIM

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/518 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a first conductive pattern on a substrate, a second conductive pattern surrounding at least a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern, an upper insulating structure on the first conductive pattern and the second conductive pattern, and an upper conductive pattern extending in a vertical direction through the upper insulating structure. The upper conductive pattern includes a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction, and a vertical extension portion extending from a local region of the main plug portion toward the substrate, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern in the vertical direction.

公开(公告)号：US20230012516A1

公开(公告)日：2023-01-19

申请号：US17672033

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoontae HWANG ,  Geunwoo KIM ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L29/417 ,  H01L29/45 ,  H01L23/522

Abstract: An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.

公开(公告)号：US20240128335A1

公开(公告)日：2024-04-18

申请号：US18369236

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun YOU ,  Junki PARK ,  Sunghwan KIM ,  Wandon KIM ,  Sughyun SUNG ,  Hyunbae LEE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active region on a substrate, a plurality of channel layers spaced apart from each other, a gate structure on the substrate, a source/drain region on at least one side of the gate structure, and a contact plug connected to the source/drain region. The contact plug includes a metal-semiconductor compound layer and a barrier layer on the metal-semiconductor compound layer. The contact plug includes a first inclined surface and a second inclined surface positioned where the metal-semiconductor compound layer and the barrier layer directly contact each other. The barrier layer includes first and second ends protruding towards the gate structure. The first and second ends are positioned at a level higher than an upper surface of an uppermost channel layer. An uppermost portion of the metal-semiconductor compound layer is positioned at a level higher than an upper surface of the source/drain region.

公开(公告)号：US20220352156A1

公开(公告)日：2022-11-03

申请号：US17846177

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Wandon KIM ,  Hyunbae LEE ,  Donggon YOO ,  Dong-Chan LIM

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US20240250000A1

公开(公告)日：2024-07-25

申请号：US18468317

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyuk YIM ,  Wandon KIM ,  Hyunbae LEE ,  Hyoseok CHOI ,  Sunghwan KIM ,  Junki PARK

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including an active pattern, a source/drain pattern on the active pattern, an active contact on the source/drain pattern; a lower power line in the substrate, a lower contact that vertically connects the active contact to the lower power line, a conductive layer between the lower contact and the lower power line, and a power delivery network layer on a bottom surface of the substrate. The conductive layer may include silicon (Si) and a first element. The first element may include a transition metal or a metalloid. A concentration of the first element may decrease in a direction from the lower contact toward the lower power line.

公开(公告)号：US20220262738A1

公开(公告)日：2022-08-18

申请号：US17475506

申请日：2021-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jangeun LEE ,  Minjoo LEE ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit chip includes a base layer. A first wiring layer is disposed on the base layer and includes a plurality of first wiring structures. A second wiring layer is disposed on the first wiring layer and includes a plurality of second wiring structures. Each of the plurality of second wiring structures has a first metal layer and a second metal layer respectively having different resistivities. A third wiring layer is disposed on the second wiring layer and includes a plurality of third wiring structures. Each of the plurality of first wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of second wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of third wiring structures comprises a material different from a material of the plurality of first wiring structures.

公开(公告)号：US20220139910A1

公开(公告)日：2022-05-05

申请号：US17578982

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo KIM ,  Yoon Tae HWANG ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L27/088 ,  H01L29/49 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

公开(公告)号：US20210134793A1

公开(公告)日：2021-05-06

申请号：US16860279

申请日：2020-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo KIM ,  Yoon Tae HWANG ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L29/49

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

公开(公告)号：US20210066289A1

公开(公告)日：2021-03-04

申请号：US16851476

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Wandon KIM ,  Hyunbae LEE ,  Donggon YOO ,  Dong-Chan LIM

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/768 ,  H01L29/06

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.