公开(公告)号：US11127789B2

公开(公告)日：2021-09-21

申请号：US16887541

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na Cho ,  Bok-Yeon Won ,  Oik Kwon

IPC: H01L27/22 ,  H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  H01L43/10

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US11770937B2

公开(公告)日：2023-09-26

申请号：US17460635

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na Cho ,  Bok-Yeon Won ,  Oik Kwon

IPC: H10B61/00 ,  H01L23/528 ,  H01L23/522 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US20140057429A1

公开(公告)日：2014-02-27

申请号：US13910734

申请日：2013-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ik Oh ,  Dae-Hyun Jang ,  Seong-soo Lee ,  Han-Na Cho

IPC: H01L21/308 ,  H01L21/768

CPC classification number: H01L21/308 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76838 ,  H01L21/76885 ,  H01L27/11575 ,  H01L27/11582

Abstract: A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.

Abstract translation: 形成多层台阶图案结构的方法包括在基板上形成具有交替的绝缘夹层和牺牲层的堆叠结构。 第一光致抗蚀剂图案形成在堆叠结构上。 通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻层叠结构的部分来形成第一预备步骤图案结构。 钝化层图案形成在第一光致抗蚀剂图案和第一初步步骤图案结构的上表面上。 通过去除由钝化层图案暴露的第一光致抗蚀剂图案的侧壁部分形成第二光致抗蚀剂图案。 通过使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻暴露的绝缘夹层和下面的牺牲层来形成第二初步步骤图案结构。 可以在第二预备步骤图案结构上重复上述步骤以形成多层台阶图案结构。

公开(公告)号：US12279438B2

公开(公告)日：2025-04-15

申请号：US18452886

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na Cho ,  Bok-Yeon Won ,  Oik Kwon

IPC: H10B61/00 ,  H01L23/522 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US10529919B2

公开(公告)日：2020-01-07

申请号：US16044666

申请日：2018-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Na Cho ,  Hye-Ji Yoon ,  O-Ik Kwon

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

Abstract: A method of manufacturing an MRAM device including forming a first insulating interlayer and a lower electrode contact, the lower electrode contact extending through the first insulating interlayer; forming a lower electrode layer, a magnetic tunnel junction layer, an upper electrode layer, and a first hard mask layer on the first insulating interlayer and lower electrode contact; forming a second hard mask on the first hard mask layer; etching the first hard mask layer and upper electrode layer to form a first hard mask and upper electrode; forming a spacer on sidewalls of the upper electrode and hard masks; and etching the magnetic tunnel junction layer and the lower electrode layer to form a structure including a lower electrode and a magnetic tunnel junction pattern on the lower electrode contact, wherein a layer remains on the upper electrode after etching the magnetic tunnel junction layer and the lower electrode layer.