公开(公告)号：US11127789B2

公开(公告)日：2021-09-21

申请号：US16887541

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na Cho ,  Bok-Yeon Won ,  Oik Kwon

IPC: H01L27/22 ,  H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  H01L43/10

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US11651995B2

公开(公告)日：2023-05-16

申请号：US17026525

申请日：2020-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkuk Kim ,  Yunseung Kang ,  Oik Kwon ,  Jungik Oh ,  Sujin Jeon

IPC: H01L23/532 ,  H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/2481 ,  H01L43/12 ,  H01L45/1675 ,  H01L45/1683 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L43/02 ,  H01L45/06 ,  H01L45/141

Abstract: A memory device including a plurality of first conductive lines arranged on a substrate and spaced apart from each other in a first direction parallel to a top surface of the substrate; a plurality of capping liners on sidewalls of each of the plurality of first conductive lines, the plurality of capping liners having top surfaces at a vertical level equal to top surfaces of the plurality of first conductive lines, and bottom surfaces at a vertical level higher than bottom surfaces of the plurality of first conductive lines; and an insulating layer on the substrate, the insulating layer filling spaces between the plurality of first conductive lines and covering sidewalls of the plurality of capping liners.

公开(公告)号：US11770937B2

公开(公告)日：2023-09-26

申请号：US17460635

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na Cho ,  Bok-Yeon Won ,  Oik Kwon

IPC: H10B61/00 ,  H01L23/528 ,  H01L23/522 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US11296277B2

公开(公告)日：2022-04-05

申请号：US16589456

申请日：2019-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Ahn ,  Oik Kwon ,  Jeonghee Park ,  Kihyun Hwang

IPC: H01L43/08 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12 ,  H01L43/10

Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

公开(公告)号：US10395979B2

公开(公告)日：2019-08-27

申请号：US16015809

申请日：2018-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho Kim ,  Woohyun Lee ,  Oik Kwon ,  Sang-Kuk Kim ,  Yeonji Kim ,  Jongchul Park

IPC: H01L27/11573 ,  H01L21/768 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A semiconductor device includes a first lower insulating interlayer, a protection insulating layer, and a first upper insulating interlayer that are sequentially stacked on a substrate, and a conductive pattern penetrating the first upper insulating interlayer, the protection insulating layer; and the first lower insulating interlayer. The conductive pattern includes a line part extending in a direction parallel to an upper surface of the substrate and contact parts extending from the line part toward the substrate. The contact parts are separated from each other with an insulating pattern therebetween. The insulating pattern includes a portion of each of the first upper insulating interlayer, the protection insulating layer, and the first lower insulating interlayer. At least a portion of the insulating pattern has a stepped profile.

公开(公告)号：US11723285B2

公开(公告)日：2023-08-08

申请号：US17655589

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Ahn ,  Oik Kwon ,  Jeonghee Park ,  Kihyun Hwang

IPC: H10N50/10 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/85 ,  H10N70/00

CPC classification number: H10N50/10 ,  H10B61/00 ,  H10B63/80 ,  H10N50/01 ,  H10N50/85 ,  H10N70/063 ,  H10N70/068 ,  H10N70/841 ,  H10N70/882

Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

公开(公告)号：US11723221B2

公开(公告)日：2023-08-08

申请号：US17113609

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Kuk Kim ,  Yunseung Kang ,  Oik Kwon ,  Yeonji Kim ,  Sujin Jeon

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/84 ,  H10N70/063

Abstract: A three-dimensional (3D) semiconductor memory device including first cell stacks arranged in first and second directions; second cell stacks disposed on the first cell stacks and arranged in the first and second directions; first conductive lines extending in the first direction and provided between a substrate and the first cell stacks; common conductive lines extending in the second direction and provided between the first and second cell stacks; etch stop patterns extending in the second direction and provided between the common conductive lines and top surfaces of the first cell stacks; second conductive lines extending in the first direction and provided on the second cell stacks; and a capping pattern covering a sidewall of the common conductive lines and a sidewall of the etch stop patterns, wherein each of the common conductive lines has a second thickness greater than a first thickness of each of the first conductive lines.

公开(公告)号：US20220209103A1

公开(公告)日：2022-06-30

申请号：US17655589

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHOON AHN ,  Oik Kwon ,  Jeonghee Park ,  Kihyun Hwang

IPC: H01L43/08 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12 ,  H01L43/10

Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

公开(公告)号：US10396277B2

公开(公告)日：2019-08-27

申请号：US15970963

申请日：2018-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woohyun Lee ,  Sang-Kuk Kim ,  Oik Kwon ,  Inho Kim ,  Jongchul Park ,  Kwangyoung Oh

IPC: H01L43/08 ,  H01F10/32 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L27/108 ,  H01L43/10

Abstract: A magnetic memory device includes a lower interlayer insulating layer on a substrate, and a plurality of magnetic tunnel junction patterns on the lower interlayer insulating layer and isolated from direct contact with each other in a direction extending parallel to a top surface of the substrate. The lower interlayer insulating layer includes an upper surface including a recessed surface and a top surface, the recessed surface at least partially defining an inner sidewall and a bottom surface of a recess region between adjacent magnetic tunnel junction patterns, such that the recessed surface at least partially defines the recess region. The inner sidewall is inclined at an acute angle with respect to the top surface of the substrate, and the bottom surface has a shape that is convex toward the top surface of the substrate, in direction extending perpendicular to the top surface of the substrate.