公开(公告)号：US20130146990A1

公开(公告)日：2013-06-13

申请号：US13668639

申请日：2012-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-sook PARK

IPC: H01L27/105

CPC classification number: H01L27/105 ,  H01L27/1052 ,  H01L29/66628

Abstract: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.

Abstract translation: 本发明的实施例提供一种半导体集成电路器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底的单元阵列区域和外围电路区域中形成多个预选栅电极结构; 在电池阵列区域和外围区域中的半导体衬底上形成选择性外延膜; 将杂质注入到至少一些选择性外延膜中以在电池阵列区域和外围电路区域中形成升高的源极/漏极区域; 形成第一层间绝缘膜; 以及图案化所述第一层间绝缘膜以形成暴露所述升高的源极/漏极区域的多个第一开口。 该方法还包括形成第一欧姆膜，第一阻挡膜和金属膜; 以及去除金属膜，第一阻挡膜和第一欧姆膜中的每一个的部分。

公开(公告)号：US20180019125A1

公开(公告)日：2018-01-18

申请号：US15651068

申请日：2017-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-won YU ,  Hyun-suk LEE ,  Ji-woon PARK ,  Gi-hee CHO ,  Hee-sook PARK ,  Woong-hee SOHN

IPC: H01L21/205 ,  H01L21/54 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/205 ,  C23C16/045 ,  C23C16/4408 ,  C23C16/45527 ,  H01L21/54 ,  H01L21/67017 ,  H01L21/6719 ,  H01L21/67739 ,  H01L21/67769

Abstract: A method of manufacturing a semiconductor device, the method including supplying a first reactant to inside a processing chamber into which a substrate has been introduced; controlling a flow of a first purge gas and storing the first purge gas, of which flow has been controlled, in a first storage for a given time period; supplying the first purge gas from the first storage to the inside of the processing chamber after supplying the first reactant; and supplying a second reactant to the inside of the processing chamber after supplying the first purge gas.

公开(公告)号：US20170309491A1

公开(公告)日：2017-10-26

申请号：US15369202

申请日：2016-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-ku AHN ,  Ji-hoon KIM ,  Seong-hun PARK ,  Youn-jae CHO ,  Hee-sook PARK ,  Woong-hee SOHN

IPC: H01L21/285 ,  C23C16/06 ,  H01L27/108

CPC classification number: H01L21/28562 ,  C23C16/0281 ,  C23C16/045 ,  C23C16/06 ,  C23C16/14 ,  C23C16/45527 ,  H01L21/28568 ,  H01L21/76877 ,  H01L27/10891

Abstract: A method of forming a tungsten film including disposing a substrate inside a process chamber; performing a tungsten nucleation layer forming operation for forming a tungsten nucleation layer on the substrate, performing a first operation for forming a portion of a tungsten bulk layer on the tungsten nucleation layer by alternately supplying a tungsten-containing gas and a reducing gas into the process chamber, and performing a second operation for stopping the supply of the tungsten-containing gas and the reducing gas and removing a remaining gas in the process chamber may be provided. The first operation and the second operation may be repeated at least twice until the tungsten bulk layer reaches a desired thickness.

公开(公告)号：US20150017797A1

公开(公告)日：2015-01-15

申请号：US14501492

申请日：2014-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-hwa PARK ,  Man-sug KANG ,  Hee-sook PARK ,  Woong-hee SOHN

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/28562 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76876 ,  H01L21/76883 ,  H01L27/10891

Abstract: A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction.

Abstract translation: 半导体器件包括：其中具有沟槽的半导体衬底，含有金属的阻挡层，沿着沟槽的内壁延伸并限定沟槽中的布线空间，布线空间沿第一方向具有第一宽度， 在配线空间中的含金属阻挡层上的含有金属的导电线，沿着第一方向包含至少一个具有大致第一宽度的粒径的金属粒子。