公开(公告)号：US11282856B2

公开(公告)日：2022-03-22

申请号：US16845615

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  HongSuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/423 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/51

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US10651191B2

公开(公告)日：2020-05-12

申请号：US15864410

申请日：2018-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  HongSuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/423 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/51

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US08962444B2

公开(公告)日：2015-02-24

申请号：US14053913

申请日：2013-10-15

Applicant: Samsung Electronics Co., Ltd

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  Hunhyeong Lim

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L21/32155 ,  H01L21/764 ,  H01L27/11524

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

Abstract translation: 提供制造半导体器件的方法。 该方法包括在衬底上形成掺杂有第一p型掺杂剂的多晶硅层，蚀刻多晶硅层和衬底以形成多晶硅图案和沟槽，从而形成覆盖层的下侧壁的器件隔离图案 沟槽中的多晶硅图案，在包括第二p型掺杂剂的气体中热处理多晶硅图案，在热处理的多晶硅图案和器件隔离图案上形成电介质层和导电层，蚀刻导电 层，电介质层和热处理的多晶硅图案，以分别形成控制栅极，电介质图案和浮置栅极。

公开(公告)号：US20150001609A1

公开(公告)日：2015-01-01

申请号：US14447746

申请日：2014-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewoong Kim ,  Junkyu Yang ,  HongSuk Kim ,  Tae-Jong Han

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/764

Abstract: Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced.

Abstract translation: 提供半导体器件及其形成方法。 半导体器件中的器件隔离结构包括间隙区域。 间隙区域中的真空或空气的介电常数小于氧化物层的介电常数，结果可能减少相邻电池之间的耦合和伴随的干扰。

公开(公告)号：US09960182B2

公开(公告)日：2018-05-01

申请号：US15634555

申请日：2017-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hoon Choi ,  SeungHyun Lim ,  Sunggil Kim ,  HongSuk Kim ,  Hunhyeong Lim ,  Hyunjun Sim

IPC: H01L27/115 ,  H01L29/10 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.

公开(公告)号：US09159737B2

公开(公告)日：2015-10-13

申请号：US14447746

申请日：2014-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewoong Kim ,  Junkyu Yang ,  HongSuk Kim ,  Tae-Jong Han

IPC: H01L29/00 ,  H01L27/115 ,  H01L21/764

CPC classification number: H01L27/11521 ,  H01L21/764

Abstract: Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced.

Abstract translation: 提供半导体器件及其形成方法。 半导体器件中的器件隔离结构包括间隙区域。 间隙区域中的真空或空气的介电常数小于氧化物层的介电常数，结果可能减少相邻电池之间的耦合和伴随的干扰。