公开(公告)号：US08785944B2

公开(公告)日：2014-07-22

申请号：US13707162

申请日：2012-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-jun Hwang ,  Jae-joon Oh ,  Jae-won Lee ,  Hyo-ji Choi ,  Jong-bong Ha

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/43

CPC classification number: H01L27/0629 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) according to example embodiments includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a reverse diode gate structure on the second semiconductor layer. A source and a drain may be on at least one of the first semiconductor layer and the second semiconductor layer. A gate electrode may be on the reverse diode gate structure.

Abstract translation: 根据示例实施例的高电子迁移率晶体管（HEMT）包括第一半导体层，第一半导体层上的第二半导体层和第二半导体层上的反向二极管栅极结构。 源极和漏极可以在第一半导体层和第二半导体层中的至少一个上。 栅电极可以在反向二极管栅极结构上。

公开(公告)号：US09209250B2

公开(公告)日：2015-12-08

申请号：US14282466

申请日：2014-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hwan Park ,  Jai-kwang Shin ,  Ki-yeol Park ,  Jae-joon Oh ,  Woo-chul Jeon ,  Hyo-ji Choi

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/1058 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Provided are high electron mobility transistors (HEMTs), methods of manufacturing the HEMTs, and electronic devices including the HEMTs. An HEMT may include an impurity containing layer, a partial region of which is selectively activated. The activated region of the impurity containing layer may be used as a depletion forming element. Non-activated regions may be disposed at opposite side of the activated region in the impurity containing layer. A hydrogen content of the activated region may be lower than the hydrogen content of the non-activated region. In another example embodiment, an HEMT may include a depletion forming element that includes a plurality of regions, and properties (e.g., doping concentrations) of the plurality of regions may be changed in a horizontal direction.

Abstract translation: 提供高电子迁移率晶体管（HEMT），制造HEMT的方法以及包括HEMT的电子器件。 HEMT可以包括含有杂质的层，其部分区域被选择性地活化。 含杂层的活化区域可以用作耗尽形成元件。 非活化区域可以设置在杂质含有层中的活化区域的相对侧。 活化区域的氢含量可能低于非活化区域的氢含量。 在另一个示例性实施例中，HEMT可以包括包含多个区域的耗尽形成元件，并且可以在水平方向上改变多个区域的特性（例如，掺杂浓度）。

公开(公告)号：US09202878B2

公开(公告)日：2015-12-01

申请号：US13713415

申请日：2012-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jo Tak ,  Jae-kyun Kim ,  Jun-youn Kim ,  Jae-won Lee ,  Hyo-ji Choi

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/267 ,  H01L29/20 ,  H01L21/02 ,  H01L29/16 ,  H01L33/12 ,  H01L33/00

CPC classification number: H01L29/267 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/0254 ,  H01L29/16 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/12

Abstract: A gallium nitride based semiconductor device includes a silicon-based layer doped simultaneously with boron (B) and germanium (Ge) at a relatively high concentration, a buffer layer on the silicon-based layer, and a nitride stack on the buffer layer. A doping concentration of boron (B) and germanium (Ge) may be higher than 1×1019/cm3.

Abstract translation: 氮化镓基半导体器件包括以相对高的浓度与硼（B）和锗（Ge）同时掺杂的硅基层，硅基层上的缓冲层和缓冲层上的氮化物叠层。 硼（B）和锗（Ge）的掺杂浓度可高于1×1019 / cm3。

公开(公告)号：US09076850B2

公开(公告)日：2015-07-07

申请号：US13953165

申请日：2013-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-jun Hwang ,  Hyo-ji Choi ,  Jong-seob Kim ,  Jae-joon Oh

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/36 ,  H01L29/423 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L29/06 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/7787

Abstract: According to example embodiments, a high electron mobility transistor includes: a channel layer including a 2-dimensional electron gas (2DEG); a contact layer on the channel layer; a channel supply layer on the contact layer; a gate electrode on a portion of the channel layer; and source and drain electrodes on at least one of the channel layer, the contact layer, and the channel supply layer. The contact layer is configured to form an ohmic contact on the channel layer. The contact layer is n-type doped and contains a Group III-V compound semiconductor. The source electrode and the drain electrode are spaced apart from opposite sides of the gate electrode.

Abstract translation: 根据示例性实施例，高电子迁移率晶体管包括：包括二维电子气（2DEG）的沟道层; 沟道层上的接触层; 接触层上的沟道供应层; 沟道层的一部分上的栅电极; 以及在沟道层，接触层和沟道供应层中的至少一个上的源极和漏极。 接触层被配置为在沟道层上形成欧姆接触。 接触层为n型掺杂并含有III-V族化合物半导体。 源电极和漏电极与栅电极的相对侧间隔开。

公开(公告)号：US08946773B2

公开(公告)日：2015-02-03

申请号：US13835704

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jo Tak ,  Jae-kyun Kim ,  Joo-sung Kim ,  Jun-youn Kim ,  Jae-won Lee ,  Hyo-ji Choi

IPC: H01L29/267 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/267 ,  G11C11/161 ,  H01L21/02104 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/2003

Abstract: A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlxInyGa1-x-yN (0≦x≦1, 0≦y≦1, 0≦x+y≦1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlxInyGa1-x-yN (0≦x

Abstract translation: 半导体缓冲结构可以包括硅衬底和形成在硅衬底上的缓冲层。 缓冲层可以包括第一层，形成在第一层上的第二层和形成在第二层上的第三层。 第一层可以包括比硅衬底的晶格常数LP0小的晶格常数LP1的Al x In y Ga 1-x-y N（0＆n 1; x＆n 1; 1,0＆amp; n 1; y＆n 1 E; 1,0＆ 第二层可以包括Al x In y Ga 1-x-y N（0＆nlE; x <1,0＆lt; nlE; y <1,0＆amp; nlE; x + y <1），并且具有大于晶格常数LP1并且小于晶格的晶格常数LP2 常数LP0。 第三层可以包括Al x In y Ga 1-x-y N（0＆nlE; x <1,0＆lt; nlE; y <1,0＆amp; nlE; x + y <1），并且具有大于晶格常数LP1并且小于晶格的晶格常数LP3 常数LP2。