公开(公告)号：US20200051632A1

公开(公告)日：2020-02-13

申请号：US16454713

申请日：2019-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-kook Park

IPC: G11C13/00

Abstract: A resistive memory device includes a memory cell array including a memory cell connected between a first signal line and a second signal line, an instance of control circuitry configured to generate a write control signal to control a data writing operation performed on the memory cell and a read control signal to control a data reading operation of reading data stored in the memory cell, a write circuit configured to supply a write current to support the data writing operation, a read circuit configured to supply a read current to support the data reading operation, a column decoder circuit configured to electrically connect the write circuit to the first signal line, based on the write control signal; and a row decoder circuit configured to electrically connect the read circuit to the second signal line, based on the read control signal.

公开(公告)号：US20160055904A1

公开(公告)日：2016-02-25

申请号：US14716166

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-kook Park ,  Chi-weon Yoon ,  Yeong-taek Lee ,  Dae-seok Byeon

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

Abstract: In a method of operating a memory device having a cross point array structure, the memory device includes multiple tiles, and each of the tiles includes memory cells of multiple layers. The method includes accessing, in a first tile, multiple memory cells of a first layer disposed in a region where at least one first line and at least one second line cross each other, accessing, in the first tile, multiple memory cells of a second layer disposed in a region where at least one first line and at least one second line cross each other, and accessing, after the memory cells of the multiple layers of the first tile are accessed, multiple memory cells included in a second tile. Related memory devices and memory systems are also discussed.

Abstract translation: 在操作具有交叉点阵列结构的存储器件的方法中，存储器件包括多个瓦片，并且每个瓦片包括多个层的存储器单元。 该方法包括：在第一瓦片中，访问第一层的多个存储单元，该第一层设置在至少一条第一线和至少一条第二条线交叉的区域中，在第一瓦片中，在第一瓦片中访问第二层的多个存储器单元 层，其设置在至少一条第一线和至少一条第二条线彼此交叉的区域中，并且在第一瓦片的多个层的存储单元被访问之后，访问包括在第二瓦片中的多个存储器单元。 还讨论了相关的存储器件和存储器系统。

公开(公告)号：US09728252B2

公开(公告)日：2017-08-08

申请号：US14796131

申请日：2015-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-kyu Lee ,  Yeong-taek Lee ,  Dae-seok Byeon ,  In-gyu Baek ,  Man Chang ,  Lijie Zhang ,  Hyun-kook Park

IPC: G11C7/04 ,  G11C13/00 ,  G11C11/56 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C11/1673 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0054

Abstract: A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.

公开(公告)号：US09269430B1

公开(公告)日：2016-02-23

申请号：US14716166

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-kook Park ,  Chi-weon Yoon ,  Yeong-taek Lee ,  Dae-seok Byeon

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

Abstract: In a method of operating a memory device having a cross point array structure, the memory device includes multiple tiles, and each of the tiles includes memory cells of multiple layers. The method includes accessing, in a first tile, multiple memory cells of a first layer disposed in a region where at least one first line and at least one second line cross each other, accessing, in the first tile, multiple memory cells of a second layer disposed in a region where at least one first line and at least one second line cross each other, and accessing, after the memory cells of the multiple layers of the first tile are accessed, multiple memory cells included in a second tile. Related memory devices and memory systems are also discussed.

Abstract translation: 在操作具有交叉点阵列结构的存储器件的方法中，存储器件包括多个瓦片，并且每个瓦片包括多个层的存储器单元。 该方法包括：在第一瓦片中，访问第一层的多个存储单元，该第一层设置在至少一条第一线和至少一条第二条线交叉的区域中，在第一瓦片中，在第一瓦片中访问第二层的多个存储器单元 层，其设置在至少一条第一线和至少一条第二条线彼此交叉的区域中，并且在第一瓦片的多个层的存储单元被访问之后，访问包括在第二瓦片中的多个存储器单元。 还讨论了相关的存储器件和存储器系统。