公开(公告)号：US20160055904A1

公开(公告)日：2016-02-25

申请号：US14716166

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-kook Park ,  Chi-weon Yoon ,  Yeong-taek Lee ,  Dae-seok Byeon

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

Abstract: In a method of operating a memory device having a cross point array structure, the memory device includes multiple tiles, and each of the tiles includes memory cells of multiple layers. The method includes accessing, in a first tile, multiple memory cells of a first layer disposed in a region where at least one first line and at least one second line cross each other, accessing, in the first tile, multiple memory cells of a second layer disposed in a region where at least one first line and at least one second line cross each other, and accessing, after the memory cells of the multiple layers of the first tile are accessed, multiple memory cells included in a second tile. Related memory devices and memory systems are also discussed.

Abstract translation: 在操作具有交叉点阵列结构的存储器件的方法中，存储器件包括多个瓦片，并且每个瓦片包括多个层的存储器单元。 该方法包括：在第一瓦片中，访问第一层的多个存储单元，该第一层设置在至少一条第一线和至少一条第二条线交叉的区域中，在第一瓦片中，在第一瓦片中访问第二层的多个存储器单元 层，其设置在至少一条第一线和至少一条第二条线彼此交叉的区域中，并且在第一瓦片的多个层的存储单元被访问之后，访问包括在第二瓦片中的多个存储器单元。 还讨论了相关的存储器件和存储器系统。

公开(公告)号：USRE46665E1

公开(公告)日：2018-01-09

申请号：US14945350

申请日：2015-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Tae Park ,  Yeong-taek Lee

IPC: G11C11/34 ,  G11C16/34

CPC classification number: G11C16/3418

Abstract: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

公开(公告)号：US09514813B2

公开(公告)日：2016-12-06

申请号：US14724909

申请日：2015-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-kyu Lee ,  Yeong-taek Lee ,  Dae-seok Byeon ,  In-gyu Baek ,  Man Chang ,  Lijie Zhang

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/04 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0088 ,  G11C2013/0092

Abstract: A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing to a memory cell based on the temperature, setting a level of a reset voltage for reset writing to the memory cell based on the temperature, and performing a write operation on the memory cell based on the level of the set voltage or current and the level of the reset voltage. The memory device may be a resistive memory device.

Abstract translation: 一种用于操作存储器件的方法包括：感测电阻性存储器件的温度，根据温度设置用于写入存储器单元的设定电压或电流的电平，设置用于复位写入的复位电压的电平到存储器 基于温度，并且基于设定电压或电流的电平以及复位电压的电平对存储器单元执行写入操作。 存储器件可以是电阻式存储器件。

公开(公告)号：USRE46994E1

公开(公告)日：2018-08-14

申请号：US14940288

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

IPC: G11C16/04 ,  G11C16/34

CPC classification number: G11C16/3418

Abstract: Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.

公开(公告)号：US09728252B2

公开(公告)日：2017-08-08

申请号：US14796131

申请日：2015-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-kyu Lee ,  Yeong-taek Lee ,  Dae-seok Byeon ,  In-gyu Baek ,  Man Chang ,  Lijie Zhang ,  Hyun-kook Park

IPC: G11C7/04 ,  G11C13/00 ,  G11C11/56 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C11/1673 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0054

Abstract: A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.

公开(公告)号：US09627056B2

公开(公告)日：2017-04-18

申请号：US15009814

申请日：2016-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-hui Park ,  Yeong-taek Lee ,  Dae-seok Byeon

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C11/5642 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2211/5645

Abstract: A resistive memory device comprising: a memory cell having a programmable resistance representing stored data; and a read circuit configured to be connected to the memory cell via a first signal line and read the stored data, wherein the read circuit includes: a voltage controller configured to control a first voltage of the first signal line to be a constant voltage and output a signal to a sensing node; and a sense amplifier connected to the voltage controller via the sensing node, and configured to compare a sensing voltage of the sensing node with a reference voltage.

公开(公告)号：US09269430B1

公开(公告)日：2016-02-23

申请号：US14716166

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-kook Park ,  Chi-weon Yoon ,  Yeong-taek Lee ,  Dae-seok Byeon

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

Abstract: In a method of operating a memory device having a cross point array structure, the memory device includes multiple tiles, and each of the tiles includes memory cells of multiple layers. The method includes accessing, in a first tile, multiple memory cells of a first layer disposed in a region where at least one first line and at least one second line cross each other, accessing, in the first tile, multiple memory cells of a second layer disposed in a region where at least one first line and at least one second line cross each other, and accessing, after the memory cells of the multiple layers of the first tile are accessed, multiple memory cells included in a second tile. Related memory devices and memory systems are also discussed.

Abstract translation: 在操作具有交叉点阵列结构的存储器件的方法中，存储器件包括多个瓦片，并且每个瓦片包括多个层的存储器单元。 该方法包括：在第一瓦片中，访问第一层的多个存储单元，该第一层设置在至少一条第一线和至少一条第二条线交叉的区域中，在第一瓦片中，在第一瓦片中访问第二层的多个存储器单元 层，其设置在至少一条第一线和至少一条第二条线彼此交叉的区域中，并且在第一瓦片的多个层的存储单元被访问之后，访问包括在第二瓦片中的多个存储器单元。 还讨论了相关的存储器件和存储器系统。