公开(公告)号：US09780033B2

公开(公告)日：2017-10-03

申请号：US15053182

申请日：2016-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changseop Yoon ,  Kwangsub Yoon ,  Jongmil Youn ,  Hyung Jong Lee

IPC: H01L23/528 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/02 ,  H01L23/485

CPC classification number: H01L23/5283 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/0653

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

公开(公告)号：US10096546B2

公开(公告)日：2018-10-09

申请号：US15704049

申请日：2017-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changseop Yoon ,  Kwangsub Yoon ,  Jongmil Youn ,  Hyung Jong Lee

IPC: H01L23/528 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/02 ,  H01L23/485

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

公开(公告)号：US12288788B2

公开(公告)日：2025-04-29

申请号：US17410326

申请日：2021-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal Lee ,  Jinwook Kim ,  Dongbeen Kim ,  Deokhan Bae ,  Junghoon Seo ,  Myungyoon Um ,  Jongmil Youn ,  Yonggi Jeong

IPC: H01L27/088 ,  H01L23/50

Abstract: An integrated circuit device includes substrate including a fin-type active area extending on the substrate in a first direction parallel to an upper surface of the substrate, a first gate line crossing the fin-type active area on the substrate and extending in a second direction perpendicular to the first direction, a cut gate line extending in the second direction and being spaced apart from the first gate line with a first gate cut area therebetween, a second gate line extending in the second direction and being spaced apart from the cut gate line with a second gate cut area therebetween, and a power wiring disposed on the cut gate line.

公开(公告)号：US10128243B2

公开(公告)日：2018-11-13

申请号：US14955107

申请日：2015-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min Yoo ,  Sangyoon Kim ,  Woosik Kim ,  Jongmil Youn ,  Hwasung Rhee ,  Heedon Jeong

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.

公开(公告)号：US10211156B2

公开(公告)日：2019-02-19

申请号：US16119475

申请日：2018-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changseop Yoon ,  Kwangsub Yoon ,  Jongmil Youn ,  Hyung Jong Lee

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/485 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

公开(公告)号：US09576613B2

公开(公告)日：2017-02-21

申请号：US14571634

申请日：2014-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Steve Sunhom Paak ,  Kangwook Park ,  Heonjong Shin ,  Sunil Yu ,  Jongmil Youn ,  Hyungsoon Jang

IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  G11C29/12 ,  G11C29/48 ,  G11C29/56

CPC classification number: G11C5/06 ,  G11C5/02 ,  G11C5/025 ,  G11C8/14 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/5602

Abstract: A semiconductor device may include a semiconductor substrate; a test circuit array region; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region, transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction, source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors, and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to drain electrodes of the transistors.

Abstract translation: 半导体器件可以包括半导体衬底; 测试电路阵列区域; 半导体衬底上的焊盘区域和测试电路阵列区域的至少第一侧以及测试电路阵列区域的外部，在第一方向和垂直于第一方向的第二方向上布置在测试电路阵列区域中的晶体管 在第二方向上彼此间隔开的源极线，每个源极线在第一方向上延伸并且电连接到晶体管的相应源电极，以及在第二方向彼此间隔开的漏极线， 漏极线在第一方向上延伸并电连接到晶体管的漏电极。