公开(公告)号：US09653572B2

公开(公告)日：2017-05-16

申请号：US14806304

申请日：2015-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seon-Ah Nam ,  Sung-Hoon Kim ,  Il-Ryong Kim ,  Kwang-You Seo ,  Kwang-Yong Jang

IPC: H01L21/3213 ,  H01L29/66 ,  H01L21/321 ,  H01L29/51 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66545 ,  H01L21/32105 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device includes forming a dummy gate on a substrate, forming a dummy gate mask on the dummy gate, forming a gate spacer on the substrate, the gate spacer covering at least one sidewall surface of the dummy gate and the dummy gate mask, forming a recess on at least one side of the dummy gate by etching the substrate, and forming an epitaxial layer in the recess using an epitaxial growth process. The forming of the dummy gate mask includes forming an oxide layer and a dummy gate mask layer on the dummy gate.

公开(公告)号：US09461132B2

公开(公告)日：2016-10-04

申请号：US14511193

申请日：2014-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keon-Yong Cheon ,  Il-Ryong Kim ,  Dong-Won Kim

IPC: H01L21/70 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/42372 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

Abstract: Provided is a semiconductor device having mid-gap work function metal gate electrodes. The semiconductor device includes a plurality of gate patterns, and the gate patterns have different gate electrode metals from each other or different gate electrode metal thicknesses from each other.

Abstract translation: 提供了具有中间功函数金属栅电极的半导体器件。 半导体器件包括多个栅极图案，并且栅极图案具有彼此不同的栅电极金属或彼此不同的栅电极金属厚度。

公开(公告)号：US10020231B2

公开(公告)日：2018-07-10

申请号：US15443498

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Hee Jeon ,  Eun-Kyoung Kwon ,  Il-Ryong Kim ,  Han-Gu Kim ,  Woo-Jin Seo ,  Ki-Tae Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L23/535 ,  H01L21/02 ,  H01L21/768 ,  H01L21/266 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0288 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.