公开(公告)号：US20170125378A1

公开(公告)日：2017-05-04

申请号：US15404090

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul PARK ,  Kilsoo KIM ,  In LEE

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48147 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.

公开(公告)号：US20240071997A1

公开(公告)日：2024-02-29

申请号：US18308358

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonghyun BAEK ,  In LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48139 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4917 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: A semiconductor package includes: a substrate that includes a wiring circuit; an interposer on the substrate, wherein the interposer includes a first side and a second side opposing each other and a third side and a fourth side between the first side and the second side, and wherein the interposer includes an interconnect circuit electrically connected to the wiring circuit; a first and second buffer chips on the interposer; a first chip stack adjacent to the first side of the interposer and connected to the first buffer chip; a second chip stack adjacent to the second side of the interposer and connected to the second buffer chip; a third chip stack adjacent to the third side of the interposer, and wherein the third chip stack includes first and second groups of semiconductor chips, which are electrically connected to the first and second buffer chips, respectively, via the interconnect circuit.

公开(公告)号：US20130299978A1

公开(公告)日：2013-11-14

申请号：US13836937

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In LEE ,  Kilsoo KIM

IPC: H05K1/02 ,  H01L23/498

CPC classification number: H05K1/0298 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4608 ,  H05K2201/10416 ,  H01L2924/00

Abstract: A wiring board and a semiconductor package are provided. The wiring board includes: a metal core including a first surface and a second surface opposite the first surface; a first buildup portion and a second buildup portion including an insulating layer and a pad pattern sequentially stacked, the first and second buildup portions being provided on the first surface and the second surface, respectively; a mask pattern including an opening exposing the pad pattern, the mask pattern being provided on the second buildup portion; and a bather pattern in an area in which a region of the metal core which overlaps with the pad pattern of the second buildup portion is removed, wherein a minimum width of an outer circumference of the barrier pattern is greater than a maximum width of the pad pattern of the second buildup portion.

Abstract translation: 提供了布线板和半导体封装。 布线板包括：金属芯，包括第一表面和与第一表面相对的第二表面; 第一累积部分和第二累积部分，其包括依次层叠的绝缘层和焊盘图案，所述第一和第二累积部分别分别设置在所述第一表面和所述第二表面上; 掩模图案，包括露出所述焊盘图案的开口，所述掩模图案设置在所述第二堆积部分上; 以及在其中去除与第二积累部分的垫图案重叠的金属芯的区域的区域中的沐浴图案，其中阻挡图案的外周的最小宽度大于垫的最大宽度 第二累积部分的图案。