公开(公告)号：US20240355879A1

公开(公告)日：2024-10-24

申请号：US18475322

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG MIN SONG ,  JAEHONG LEE ,  KANG-ILL SEO

IPC: H01L29/06 ,  H01L25/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L25/117 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device comprising: an upper transistor structure on a substrate, the upper transistor structure comprising a pair of upper source/drain regions spaced apart from each other in a first horizontal direction and an upper gate electrode between the pair of upper source/drain regions; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower gate electrode; an upper insulating layer on the lower transistor structure, wherein the upper gate electrode is in the upper insulating layer; and a lower gate contact extending through the upper insulating layer and contacting the lower gate electrode, a center of the upper gate electrode in a second horizontal direction and a center of the lower gate electrode in the second horizontal direction are offset from each other in the second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction.

公开(公告)号：US20250151389A1

公开(公告)日：2025-05-08

申请号：US18763180

申请日：2024-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGCHAN YUN ,  JAEHONG LEE ,  MYUNG YANG ,  KANG-ILL SEO

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Stacked field-effect transistor (FET) devices are provided. A stacked FET device includes a lower FET having lower channel layers and a lower work-function metal (WFM) layer that is between the lower channel layers. The stacked FET device includes an upper FET that is on top of the lower FET. The upper FET has upper channel layers and an upper WFM layer that is between the upper channel layers. Moreover, the stacked FET device includes an insulating capping layer that is on the upper WFM layer. Related methods of forming stacked FET devices are also provided.

公开(公告)号：US20250062192A1

公开(公告)日：2025-02-20

申请号：US18805631

申请日：2024-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEHONG LEE ,  SOOYOUNG PARK ,  WONHYUK HONG ,  KANG-ILL SEO

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/07 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same. As an example, an integrated circuit device may include a substrate; a first transistor structure on the substrate; a second transistor structure stacked in a vertical direction on the first transistor structure; an isolation layer between the first transistor structure and the second transistor structure in the vertical direction; and a diode structure on the substrate and adjacent to the first transistor structure in a horizontal direction. The diode structure may be part of a discharging path between a gate electrode of the second transistor structure and the substrate. The discharging path may extend through the isolation layer.

公开(公告)号：US20250063825A1

公开(公告)日：2025-02-20

申请号：US18735681

申请日：2024-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEHONG LEE ,  WONHYUK HONG ,  KANG-ILL SEO

IPC: H01L27/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same. As an example, an integrated circuit device may include a first substrate; a first transistor structure on the substrate; a second transistor structure stacked in a vertical direction on the first transistor structure; an isolation layer between the first transistor structure and the second transistor structure in the vertical direction; a diode structure on the first substrate and adjacent to the first transistor structure in a horizontal direction; and a second substrate on the second transistor structure in the vertical direction. The diode structure may be part of a discharging path between a gate electrode of the second transistor structure and the second substrate. The discharging path may extend through the isolation layer.