公开(公告)号：US20240079329A1

公开(公告)日：2024-03-07

申请号：US18162920

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUN SUNG KIM ,  JAE YOUNG CHOI ,  WONHYUK HONG ,  SEUNGCHAN YUN ,  JAEJIK BAEK ,  SEUNG MIN SONG ,  KANG-ILL SEO

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/535

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a sacrificial layer in a preliminary substrate by adding an element into the preliminary substrate, forming a transistor structure on the preliminary substrate, the transistor structure including a source/drain region, replacing the sacrificial layer with a power contact that comprises an upper surface contacting the source/drain region, and forming a power rail that contacts a lower surface of the power contact.

公开(公告)号：US20240063122A1

公开(公告)日：2024-02-22

申请号：US18147739

申请日：2022-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGCHAN YUN ,  WONHYUK HONG ,  JAEJIK BAEK ,  EUN SUNG KIM ,  KANG-ILL SEO

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/401 ,  H01L29/66439

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including a channel region and a source/drain region contacting the channel region, a power rail that is configured be electrically connected to a power source and is spaced apart from the source/drain region in a first direction, and a power contact that is between the source/drain region and the power rail and contacts both the source/drain region and the power rail. The channel region may overlap the power contact in the first direction.

公开(公告)号：US20250169186A1

公开(公告)日：2025-05-22

申请号：US18642910

申请日：2024-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： KEUMSEOK PARK ,  SEUNGCHAN YUN ,  KANG-ILL SEO

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775

Abstract: Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes a semiconductor spacer between the upper transistor and the lower transistor. Related methods of forming transistor devices are also provided.

公开(公告)号：US20250151389A1

公开(公告)日：2025-05-08

申请号：US18763180

申请日：2024-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGCHAN YUN ,  JAEHONG LEE ,  MYUNG YANG ,  KANG-ILL SEO

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Stacked field-effect transistor (FET) devices are provided. A stacked FET device includes a lower FET having lower channel layers and a lower work-function metal (WFM) layer that is between the lower channel layers. The stacked FET device includes an upper FET that is on top of the lower FET. The upper FET has upper channel layers and an upper WFM layer that is between the upper channel layers. Moreover, the stacked FET device includes an insulating capping layer that is on the upper WFM layer. Related methods of forming stacked FET devices are also provided.

公开(公告)号：US20240371880A1

公开(公告)日：2024-11-07

申请号：US18460110

申请日：2023-09-01

Applicant: Samsung Electronics Co, Ltd.

Inventor： SEUNGCHAN YUN ,  Jaejik Baek ,  KANG-ILL Seo

IPC: H01L27/12 ,  H01L21/84

Abstract: An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.

公开(公告)号：US20240363491A1

公开(公告)日：2024-10-31

申请号：US18240675

申请日：2023-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGCHAN YUN ,  WONHYUK HONG ,  PANJAE PARK ,  KANG-ILL SEO

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor comprising a source/drain region on a substrate; a backside power rail spaced apart from the source/drain region; and a power contact that is between the source/drain region and the backside power rail and electrically connects the source/drain region to the backside power rail. The substrate may be between the source/drain region and the backside power rail, and a centerline in a width direction of the source/drain region is angled with respect to a centerline in a width direction of the power contact.

公开(公告)号：US20210175352A1

公开(公告)日：2021-06-10

申请号：US17026551

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGHWAN HAN ,  SEUNGCHAN YUN

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate including an active region that extends in a first direction; a gate structure that intersects the active region and that extends in a second direction; a source/drain region on the active region on at least one side of the gate structure; a contact plug on the source/drain region on the at least one side of the gate structure; and a contact insulating layer on sidewalls of the contact plug, wherein a lower end of the contact plug is closer to the substrate than a lower end of the source/drain region.