公开(公告)号：US20240355878A1

公开(公告)日：2024-10-24

申请号：US18456571

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG MIN SONG ,  Panjae Park ,  Kang-Ill Seo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L25/07 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L25/074 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices may include an upper transistor structure on a substrate, the upper transistor structure comprising an upper channel region and an upper gate electrode on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower channel region and a lower gate electrode on the lower channel region; and an intergate contact between the lower gate electrode and the upper gate electrode. The lower gate electrode may be electrically connected to the upper gate electrode through the intergate contact, and a portion of a lower surface of the intergate contact may protrude beyond a side surface of the lower gate electrode.

公开(公告)号：US20250133801A1

公开(公告)日：2025-04-24

申请号：US18611923

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG YANG ,  SEUNG MIN SONG ,  KANG-ILL SEO

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Transistor devices are provided. A transistor device includes a substrate and a transistor stack including first and second transistors on the substrate. The first transistor or the second transistor includes a plurality of semiconductor channel layers, a gate on the plurality of semiconductor channel layers, and an insulating spacer that is on a sidewall of the gate and between the plurality of semiconductor channel layers. Moreover, the insulating spacer includes: a first portion on a sidewall of the gate; and a second portion that is spaced apart from the sidewall of the gate by the first portion, and that has a lower dielectric constant than the first portion. Related methods of forming transistor devices are also provided.

公开(公告)号：US20180261668A1

公开(公告)日：2018-09-13

申请号：US15726535

申请日：2017-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG GIL YANG ,  SEUNG MIN SONG ,  SUNG MIN KIM ,  WOO SEOK PARK ,  GEUM JONG BAE ,  DONG IL BAE

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78645

Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.

公开(公告)号：US20240355879A1

公开(公告)日：2024-10-24

申请号：US18475322

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG MIN SONG ,  JAEHONG LEE ,  KANG-ILL SEO

IPC: H01L29/06 ,  H01L25/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L25/117 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device comprising: an upper transistor structure on a substrate, the upper transistor structure comprising a pair of upper source/drain regions spaced apart from each other in a first horizontal direction and an upper gate electrode between the pair of upper source/drain regions; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower gate electrode; an upper insulating layer on the lower transistor structure, wherein the upper gate electrode is in the upper insulating layer; and a lower gate contact extending through the upper insulating layer and contacting the lower gate electrode, a center of the upper gate electrode in a second horizontal direction and a center of the lower gate electrode in the second horizontal direction are offset from each other in the second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction.

公开(公告)号：US20240079329A1

公开(公告)日：2024-03-07

申请号：US18162920

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUN SUNG KIM ,  JAE YOUNG CHOI ,  WONHYUK HONG ,  SEUNGCHAN YUN ,  JAEJIK BAEK ,  SEUNG MIN SONG ,  KANG-ILL SEO

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/535

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a sacrificial layer in a preliminary substrate by adding an element into the preliminary substrate, forming a transistor structure on the preliminary substrate, the transistor structure including a source/drain region, replacing the sacrificial layer with a power contact that comprises an upper surface contacting the source/drain region, and forming a power rail that contacts a lower surface of the power contact.

公开(公告)号：US20170358665A1

公开(公告)日：2017-12-14

申请号：US15361110

申请日：2016-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNG MIN SONG ,  DONG CHAN SUH ,  JUNG GIL YANG ,  GEUM JONG BAE ,  WOO BIN SONG

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/66795 ,  H01L29/0676 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/78696

Abstract: A method of manufacturing semiconductor device includes forming a plurality of sacrificial layers and a plurality of semiconductor layers repeatedly and alternately stacked on a substrate, partially removing the sacrificial layers, forming spacers in removed regions of the sacrificial layers, and replacing remaining portions of the sacrificial layers with a gate electrode. Each of the sacrificial layers includes first portions disposed adjacent to the plurality of semiconductor layers and a second portions disposed between the first portions. The second portion having a different composition from the first portions.