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    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME
    1.
    发明申请
    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20210225418A1

    公开(公告)日：2021-07-22

    申请号：US17145941

    申请日：2021-01-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngcheon KWON ,  Jemin RYU ,  Jaeyoun YOUN ,  Haesuk LEE ,  Jihyun CHOI

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

    Electronic Device and Operating Method Thereof
    5.
    发明申请
    Electronic Device and Operating Method Thereof 审中-公开
    电子设备及其操作方法

    公开(公告)号：US20160253059A1

    公开(公告)日：2016-09-01

    申请号：US15052106

    申请日：2016-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jihyun CHOI

    IPC: G06F3/0483 ,  G06F3/0484

    CPC classification number: G06F3/0483 ,  G06F3/0488

    Abstract: According to an embodiment, a method of operating an electronic device may include selecting a first page to delete from a plurality of pages, selecting a second page from the plurality of pages to which objects included in the first page are to be moved, moving the objects included in the first page to the second page, and deleting the first page. A method of operating an electronic device is not limited to the above method, and other embodiments can be made within the same or a similar scope of the present disclosure.

    Abstract translation: 根据实施例，操作电子设备的方法可以包括：从多个页面中选择要删除的第一页面，从包括在第一页面中的对象要被移动到的多个页面中选择第二页面，移动 包括在第一页中的对​​象到第二页，以及删除第一页。 操作电子设备的方法不限于上述方法，并且可以在本公开的相同或相似的范围内进行其他实施例。

    TEST DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING TEST DEVICE
    6.
    发明申请
    TEST DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING TEST DEVICE 有权

    公开(公告)号：US20250012854A1

    公开(公告)日：2025-01-09

    申请号：US18620170

    申请日：2024-03-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jihyun CHOI ,  Seonmi LEE ,  Yonggyun KIM ,  Seongseob SHIN ,  Dahm YU ,  Dongho LEE

    IPC: G01R31/28

    Abstract: A test device includes a test board, a connector attached to a lower surface of the test board, a heating device disposed on an upper surface of the test board, the heating device configured to emit heat in response to a signal input through the connector, a temperature sensor disposed on the upper surface of the test board, the temperature sensor configured to measure a temperature of the heating device, and a test socket disposed on the upper surface of the test board, the test socket configured to transmit and receive a signal to and from the heating device and the temperature sensor. Before a test process is performed or after the test process is completed, an internal temperature of a chamber may be verified, thereby improving reliability of the test process.

    SEMICONDUCTOR DEVICE
    7.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240179890A1

    公开(公告)日：2024-05-30

    申请号：US18374870

    申请日：2023-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byunghoon CHO ,  Namjung KANG ,  Kiheum NAM ,  Jihyun CHOI

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/50

    Abstract: A semiconductor device includes a peripheral circuit transistor disposed in a peripheral circuit region. First connection lines and second connection lines are disposed on a same plane above the peripheral circuit transistor. The second connection lines including a cutting portion. A cell capacitor is disposed on the substrate in a cell region. A first plate pattern is on the cell capacitor. A second plate pattern is on a portion of a surface of the first plate pattern. A first contact plug directly contacts an upper surface of the second plate pattern. A third connection line is disposed above the second connection line. The third connection line faces the cutting portion. Second contact plugs extend vertically to directly contact both sidewalls of the third connection line and upper surfaces of the second connection lines. The third connection line is disposed on a same plane as the second plate pattern.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220122685A1

    公开(公告)日：2022-04-21

    申请号：US17313236

    申请日：2021-05-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunggi AHN ,  Yesin RYU ,  Jun Jin KONG ,  Eunae LEE ,  Jihyun CHOI

    IPC: G11C29/42 ,  G11C29/46 ,  G11C29/14 ,  G11C29/52

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.

    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220083260A1

    公开(公告)日：2022-03-17

    申请号：US17245325

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Haesuk LEE ,  Reum OH ,  Youngcheon KWON ,  Beomyong KIL ,  Jemin RYU ,  Jihyun CHOI

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

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