公开(公告)号：US20190333908A1

公开(公告)日：2019-10-31

申请号：US16506309

申请日：2019-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Won KANG ,  Jong-Joo LEE

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16

Abstract: A semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad.

公开(公告)号：US20190206797A1

公开(公告)日：2019-07-04

申请号：US16044719

申请日：2018-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Joo LEE ,  Hee-woo AN

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor memory package is provided. The package includes a base substrate, and chip connection pads and external connection pads respectively arranged on upper and lower surfaces of the base substrate; and two semiconductor memory chips mounted on the base substrate each having chip pads electrically connected to the chip connection pads. A first electrical path extends from an external connection pad to a first chip pad of one of the chips and a second electrical path extends from the external connection pad to a second chip pad of another chip, the first and second electrical paths have a common line, and the first electrical path has a first branch line and the second electrical path has a second branch line. The base substrate includes an open stub extending from the common line and having an end which is open without being connected to another electrical path.

公开(公告)号：US20180130781A1

公开(公告)日：2018-05-10

申请号：US15787434

申请日：2017-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Won KANG ,  Jong-Joo LEE

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L27/0811 ,  H01L29/945 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad.

公开(公告)号：US20140110831A1

公开(公告)日：2014-04-24

申请号：US14143178

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung KANG ,  Jong-Joo LEE ,  Yong-Hoon KIM ,  Tae-Hong MIN

IPC: H01L23/498 ,  H01L23/367

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract translation: 多芯片封装可以包括封装衬底，插入器芯片，第一半导体芯片，散热结构和第二半导体芯片。 插入器芯片可以安装在封装衬底上。 第一半导体芯片可以安装在插入器芯片上。 第一半导体芯片的尺寸可以小于插入器芯片的尺寸。 散热结构可以布置在插入器芯片上以围绕第一半导体芯片。 散热结构可以将第一半导体芯片中的热量传递到插入器芯片。 第二半导体芯片可以安装在第一半导体芯片上。 因此，可以通过散热线将第一半导体芯片中的热量有效地传递到插入器芯片。