公开(公告)号：US20150048493A1

公开(公告)日：2015-02-19

申请号：US14318643

申请日：2014-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hong MIN ,  Young-Kun JEE ,  Tae-Je CHO

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/373

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/433 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/2732 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83907 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2224/92225 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/07802

Abstract: In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability.

Abstract translation: 在一个实施例中，半导体封装包括电路基板，堆叠在电路基板上的多个半导体芯片，插入在半导体芯片之间的绝缘粘合剂图案，设置在最上半导体芯片上的散热片，并通过 散热粘合剂图案，以及设置在电路基板上以覆盖半导体芯片的侧壁，绝缘粘合剂图案，散热粘合剂图案和热块的模具结构。 在模具结构的制造过程中半导体封装的故障可能会降低。 因此，半导体封装可具有良好的工作特性和可靠性。

公开(公告)号：US20140110831A1

公开(公告)日：2014-04-24

申请号：US14143178

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung KANG ,  Jong-Joo LEE ,  Yong-Hoon KIM ,  Tae-Hong MIN

IPC: H01L23/498 ,  H01L23/367

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract translation: 多芯片封装可以包括封装衬底，插入器芯片，第一半导体芯片，散热结构和第二半导体芯片。 插入器芯片可以安装在封装衬底上。 第一半导体芯片可以安装在插入器芯片上。 第一半导体芯片的尺寸可以小于插入器芯片的尺寸。 散热结构可以布置在插入器芯片上以围绕第一半导体芯片。 散热结构可以将第一半导体芯片中的热量传递到插入器芯片。 第二半导体芯片可以安装在第一半导体芯片上。 因此，可以通过散热线将第一半导体芯片中的热量有效地传递到插入器芯片。