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    Apparatus for testing a signal speed of a semiconductor package and method of manufacturing a semiconductor package
    1.
    发明授权
    Apparatus for testing a signal speed of a semiconductor package and method of manufacturing a semiconductor package 有权

    公开(公告)号：US10816594B2

    公开(公告)日：2020-10-27

    申请号：US16046015

    申请日：2018-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-Jae Song

    IPC: G01R31/28 ,  H01L21/66

    Abstract: An apparatus for testing a signal speed of a semiconductor package may include a plurality of sockets, one or more test boards including at least a first test board, an extension board and a test head. Each of the sockets may be configured to receive the semiconductor package. The first test board may include a plurality of mount regions on which the sockets may be mounted, and test lines extended from the mount regions toward at least one side surface of the first test board. The extension board may be vertically arranged at the side surface of the first test board. The extension board may be electrically connected to the test lines. The test head may be electrically connected to the extension board to provide the mount regions with a test signal for testing the signal speed of the semiconductor package through the extension board. Thus, it may not be required to change a structure of the socket in accordance with types of the semiconductor packages.

    Package test devices having a printed circuit board
    4.
    发明授权
    Package test devices having a printed circuit board 有权
    具有印刷电路板的封装测试装置

    公开(公告)号：US08832638B2

    公开(公告)日：2014-09-09

    申请号：US13780891

    申请日：2013-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hoon Jeong ,  Chang-Woo Ko ,  Ki-Jae Song ,  Hun-Kyo Seo

    IPC: G06F17/50 ,  G01R1/04 ,  G01R31/28 ,  G11C29/56

    CPC classification number: G01R1/0408 ,  G01R31/2808 ,  G06F17/5068 ,  G11C29/56 ,  G11C2029/5602

    Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.

    Abstract translation: 在设计印刷电路板的方法中，计算实际存储器件的封装电容，封装电感和芯片电容。 基于印刷电路板的特性来计算信号线的每单位长度的信号线电容和信号线电感。 基于封装电容和信号线电容确定每个引脚的信号线的长度。

    PACKAGE TEST DEVICES HAVING A PRINTED CIRCUIT BOARD
    5.
    发明申请
    PACKAGE TEST DEVICES HAVING A PRINTED CIRCUIT BOARD 有权
    具有印刷电路板的封装测试装置

    公开(公告)号：US20130176045A1

    公开(公告)日：2013-07-11

    申请号：US13780891

    申请日：2013-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hoon Jeong ,  Chang-Woo Ko ,  Ki-Jae Song ,  Hun-Kyo Seo

    IPC: G01R1/04

    CPC classification number: G01R1/0408 ,  G01R31/2808 ,  G06F17/5068 ,  G11C29/56 ,  G11C2029/5602

    Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.

    Abstract translation: 在设计印刷电路板的方法中，计算实际存储器件的封装电容，封装电感和芯片电容。 基于印刷电路板的特性来计算信号线的每单位长度的信号线电容和信号线电感。 基于封装电容和信号线电容确定每个引脚的信号线的长度。

    Test interface board and test system including the same
    8.
    发明授权
    Test interface board and test system including the same 有权
    测试接口板和测试系统包括相同

    公开(公告)号：US09513333B2

    公开(公告)日：2016-12-06

    申请号：US14458241

    申请日：2014-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-Jae Song ,  Jong-woon Yoo

    IPC: G01R31/00 ,  G01R31/30 ,  G01R31/28 ,  G11C29/56 ,  G11C5/14

    CPC classification number: G01R31/3004 ,  G01R31/2839 ,  G01R31/2889 ,  G11C5/147 ,  G11C29/56 ,  G11C2029/5602

    Abstract: A test interface board includes a substrate including a power plane electrically connected to at least one power terminal of a semiconductor device under test, and a ground plane electrically connected to at least one ground terminal of the semiconductor device under test, and a voltage regulator arranged on the substrate and configured to supply, via the power plane and the ground plane, to the semiconductor device under test, a driving voltage.

    Abstract translation: 测试接口板包括：基板，包括电连接到被测半导体器件的至少一个电源端子的电源平面;以及电连接到被测半导体器件的至少一个接地端子的接地平面;以及电压调节器， 在基板上并经配置以经由电源平面和接地平面向被测半导体器件提供驱动电压。

    RECHARGEABLE POWER MODULE AND TEST SYSTEM INCLUDING THE SAME
    9.
    发明申请
    RECHARGEABLE POWER MODULE AND TEST SYSTEM INCLUDING THE SAME 有权
    可充电的电源模块和测试系统，包括它们

    公开(公告)号：US20160131709A1

    公开(公告)日：2016-05-12

    申请号：US14728333

    申请日：2015-06-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Woon Yoo ,  Ki-Jae Song ,  Soo-Yong Park

    IPC: G01R31/317 ,  G01R31/28 ,  H02J7/00

    CPC classification number: G01R31/31721 ,  G01R31/2834 ,  G01R31/31924 ,  H02J7/0047 ,  H02J7/008 ,  H02J2007/005

    Abstract: A rechargeable power module (RPM) may include a rechargeable energy storage device such as a battery or capacitor, a charging circuit, a direct-current (DC) to DC converter, a low drop-out (LDO) voltage regulator and a controller. The charging circuit provides the rechargeable energy storage device with a charging current based on power requirements of device under test and the state of charge, or storage, of the energy storage device.

    Abstract translation: 可再充电电源模块（RPM）可以包括诸如电池或电容器的充电能量存储装置，充电电路，直流（DC）到DC转换器，低压降（LDO）电压调节器和控制器。 充电电路为可再充电能量存储装置提供基于能量存储装置的充电状态或存储状态的充电电流。

    TEST INTERFACE BOARDS AND TEST SYSTEMS
    10.
    发明申请
    TEST INTERFACE BOARDS AND TEST SYSTEMS 审中-公开
    测试接口板和测试系统

    公开(公告)号：US20130342236A1

    公开(公告)日：2013-12-26

    申请号：US13804149

    申请日：2013-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Jae Song ,  Jong-Woon Yoo ,  Sang-Kyeong Han ,  Gil-Beag Kim

    IPC: G01R1/04

    CPC classification number: G01R1/0408 ,  G01R31/31926

    Abstract: A test interface board comprises at least one switch matrix including a plurality of switching elements that connect a plurality of connection nodes to each other. The at least one switch matrix is configured to connect a plurality of channels of an automatic test equipment (ATE) to respective pin positions corresponding to a device under test (DUT) in response to switching control signals. The plurality of channels provide test operation signals for testing the DUT. A control logic is configured to generate the switching control signals based on pin configuration information of the DUT.

    Abstract translation: 测试接口板包括至少一个开关矩阵，其包括将多个连接节点彼此连接的多个开关元件。 至少一个开关矩阵被配置为响应于开关控制信号将自动测试设备（ATE）的多个通道连接到对应于被测器件（DUT）的相应引脚位置。 多个通道提供用于测试DUT的测试操作信号。 控制逻辑被配置为基于DUT的引脚配置信息生成开关控制信号。

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