公开(公告)号：US10748617B2

公开(公告)日：2020-08-18

申请号：US16222038

申请日：2018-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kui-Han Ko ,  Jin-Young Kim ,  Il-Han Park ,  Bong-Soon Lim

IPC: G11C8/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of operating a nonvolatile memory device is provided where the nonvolatile memory device includes a plurality of cell strings, and each cell string includes a plurality of multi-level cells. a voltage of a selected word line is sequentially changed to sequentially have a plurality of read voltages for determining threshold voltage states of the plurality of multi-level cells. A voltage of an adjacent word line adjacent to the selected word line is sequentially changed in synchronization with voltage changing time points of the selected word line. A load of the selected word line is reduced and an operation speed of the nonvolatile memory device is increased by synchronizing the voltage change of the selected word line and the voltage change of the adjacent word line in the same direction.

公开(公告)号：US11961564B2

公开(公告)日：2024-04-16

申请号：US17503952

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Yeon Yu ,  Kui-Han Ko ,  Il-Han Park ,  June-Hong Park ,  Joo-Yong Park ,  Joon-Young Park ,  Bong-Soon Lim

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/0483

Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.

公开(公告)号：US11183249B2

公开(公告)日：2021-11-23

申请号：US16141147

申请日：2018-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Yeon Yu ,  Kui-Han Ko ,  Il-Han Park ,  June-Hong Park ,  Joo-Yong Park ,  Joon-Young Park ,  Bong-Soon Lim

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C11/56 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: To program in a nonvolatile memory device, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.