公开(公告)号：US10593408B2

公开(公告)日：2020-03-17

申请号：US16191656

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hong Park ,  Ki-Whan Song ,  Bong-Soon Lim ,  Su-Chang Jeon ,  Jin-Young Kim ,  Chang-Yeon Yu ,  Dong-Kyo Shim ,  Seong-Jin Kim

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C7/10 ,  G11C16/26 ,  G11C7/12 ,  G11C16/04 ,  G11C16/32

Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.

公开(公告)号：US10170192B2

公开(公告)日：2019-01-01

申请号：US15717992

申请日：2017-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hong Park ,  Ki-Whan Song ,  Bong-Soon Lim ,  Su-Chang Jeon ,  Jin-Young Kim ,  Chang-Yeon Yu ,  Dong-Kyo Shim ,  Seong-Jin Kim

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.

公开(公告)号：US11961564B2

公开(公告)日：2024-04-16

申请号：US17503952

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Yeon Yu ,  Kui-Han Ko ,  Il-Han Park ,  June-Hong Park ,  Joo-Yong Park ,  Joon-Young Park ,  Bong-Soon Lim

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/0483

Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.

公开(公告)号：US11183249B2

公开(公告)日：2021-11-23

申请号：US16141147

申请日：2018-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Yeon Yu ,  Kui-Han Ko ,  Il-Han Park ,  June-Hong Park ,  Joo-Yong Park ,  Joon-Young Park ,  Bong-Soon Lim

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C11/56 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: To program in a nonvolatile memory device, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.

公开(公告)号：US10163475B2

公开(公告)日：2018-12-25

申请号：US15647658

申请日：2017-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Yeon Yu ,  June-Hong Park ,  Seong-Jin Kim

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/12 ,  G11C7/14 ,  G11C7/18 ,  G11C8/14 ,  G11C29/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A non-volatile memory device includes a cell string, a ground select transistor, and at least one dummy cell. The cell string includes at least one memory cell. The at least one dummy cell is provided between the at least one memory cell and the ground select transistor and is connected to a bit line. A controller executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell to be lower than a threshold voltage of the at least one dummy cell in at least a part of a pre-charge period.

公开(公告)号：US09818483B2

公开(公告)日：2017-11-14

申请号：US15263724

申请日：2016-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wook-Ghee Hahn ,  Chang-Yeon Yu

IPC: G11C16/08 ,  G11C16/24 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/04 ,  G11C16/20

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/0483 ,  G11C16/20 ,  G11C16/24

Abstract: A row decoder of the semiconductor memory device includes a decoding and precharging unit that is connected between a high voltage node and a block word line, wherein the decoding and precharging unit precharges the block word line, and wherein the decoding and precharging unit includes one or more decoding transistors that decode an address and form a transmission path for transmitting a block selection voltage. The row decoder further includes a pass transistor block that transmits one or more row driving voltages to row lines in response to the block selection voltage, wherein the block selection voltage is boosted according to a switching operation of the pass transistor block.