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公开(公告)号：US11183249B2
公开(公告)日：2021-11-23
申请号：US16141147
申请日：2018-09-25
发明人： Chang-Yeon Yu , Kui-Han Ko , Il-Han Park , June-Hong Park , Joo-Yong Park , Joon-Young Park , Bong-Soon Lim
IPC分类号： G11C16/16 , G11C16/08 , G11C16/26 , G11C16/04 , G11C16/24 , G11C11/56 , G11C16/10 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： To program in a nonvolatile memory device, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.
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公开(公告)号：US10593408B2
公开(公告)日：2020-03-17
申请号：US16191656
申请日：2018-11-15
发明人： June-Hong Park , Ki-Whan Song , Bong-Soon Lim , Su-Chang Jeon , Jin-Young Kim , Chang-Yeon Yu , Dong-Kyo Shim , Seong-Jin Kim
摘要： A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
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公开(公告)号：US10163475B2
公开(公告)日：2018-12-25
申请号：US15647658
申请日：2017-07-12
发明人： Chang-Yeon Yu , June-Hong Park , Seong-Jin Kim
IPC分类号： G11C7/00 , G11C7/22 , G11C7/12 , G11C7/14 , G11C7/18 , G11C8/14 , G11C29/02 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/32
摘要： A non-volatile memory device includes a cell string, a ground select transistor, and at least one dummy cell. The cell string includes at least one memory cell. The at least one dummy cell is provided between the at least one memory cell and the ground select transistor and is connected to a bit line. A controller executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell to be lower than a threshold voltage of the at least one dummy cell in at least a part of a pre-charge period.
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4.发明授权Nonvolatile memory device, memory system having the same, external power controlling method thereof 有权非易失性存储器件，具有相同的存储器系统，其外部功率控制方法公开(公告)号：US09147488B2
公开(公告)日：2015-09-29
申请号：US14061019
申请日：2013-10-23
发明人： TaeHyun Kim , June-Hong Park , Sungwhan Seo , Jinyub Lee
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/12
摘要： An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first node; transferring a voltage of the first node to a second node in response to the flag signal; and discharging at least one voltage of an internal circuit connected to the second node in response to the flag signal.
摘要翻译： 外部功率控制方法包括根据第一外部电压的下降来确定是否向第一节点施加第二外部电压; 当第二外部电压施加到第一节点时，根据第二外部电压的下降产生标志信号; 响应于所述标志信号将所述第一节点的电压传送到第二节点; 以及响应于所述标志信号，放电连接到所述第二节点的内部电路的至少一个电压。
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公开(公告)号：US10529727B2
公开(公告)日：2020-01-07
申请号：US16165237
申请日：2018-10-19
发明人： June-Hong Park , Bong-Soon Lim
IPC分类号： G11C5/14 , H01L27/11529 , G11C16/08 , H01L27/11519 , H01L27/11565 , H01L27/1157 , H01L27/11556 , H01L27/11582 , H01L27/11573 , H01L27/11524 , G11C16/04
摘要： A nonvolatile memory device includes a plurality of gate lines extending in a first direction and stacked in a second direction to form a memory block, where the second direction is perpendicular to the first direction, an address decoder disposed at a first side of the plurality of gate lines to drive the plurality of gate lines, a voltage compensation line extending in the first direction substantially in parallel with the plurality of gate lines, and overlapping with a target gate line among the plurality of gate lines in the second direction, a rising vertical contact extending in the second direction to connect the address decoder and a first portion of the voltage compensation line, and conduction paths connecting in the second direction the first and second portions of the voltage compensation line with near and far end portions of the target gate line.
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公开(公告)号：US10170192B2
公开(公告)日：2019-01-01
申请号：US15717992
申请日：2017-09-28
发明人： June-Hong Park , Ki-Whan Song , Bong-Soon Lim , Su-Chang Jeon , Jin-Young Kim , Chang-Yeon Yu , Dong-Kyo Shim , Seong-Jin Kim
摘要： A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
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7.发明授权公开(公告)号：US09437317B2
公开(公告)日：2016-09-06
申请号：US14835230
申请日：2015-08-25
发明人： TaeHyun Kim , June-Hong Park , Sungwhan Seo , Jinyub Lee
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/12
摘要： An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first node; transferring a voltage of the first node to a second node in response to the flag signal; and discharging at least one voltage of an internal circuit connected to the second node in response to the flag signal.
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8.发明申请NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, EXTERNAL POWER CONTROLLING METHOD THEREOF 审中-公开非易失性存储器件，具有该存储器件的存储器系统，其外部功率控制方法公开(公告)号：US20150364204A1
公开(公告)日：2015-12-17
申请号：US14835230
申请日：2015-08-25
发明人： Tae Hyun KIM , June-Hong Park , Sungwhan Seo , Jin-Yub Lee
IPC分类号： G11C16/30
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/12
摘要： An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first node; transferring a voltage of the first node to a second node in response to the flag signal; and discharging at least one voltage of an internal circuit connected to the second node in response to the flag signal.
摘要翻译： 外部功率控制方法包括根据第一外部电压的下降来确定是否向第一节点施加第二外部电压; 当第二外部电压施加到第一节点时，根据第二外部电压的下降产生标志信号; 响应于所述标志信号将所述第一节点的电压传送到第二节点; 以及响应于所述标志信号，放电连接到所述第二节点的内部电路的至少一个电压。
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