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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190355744A1

    公开(公告)日：2019-11-21

    申请号：US16526139

    申请日：2019-07-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-soo KIM ,  Yong-seok KIM ,  Tae-hun KIM ,  Min-kyung BAE ,  Jae-hoon JANG ,  Kohji KANAMORI

    IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/78

    Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210391340A1

    公开(公告)日：2021-12-16

    申请号：US17459887

    申请日：2021-08-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hae-min LEE ,  Kwang-soo KIM ,  Sun-il SHIM

    IPC: H01L27/1157 ,  G11C5/06 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556

    Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

    WIRELESS NETWORK AUDIO SYSTEM HAVING AUTO-PAIRING FUNCTION AND AUTO-PAIRING METHOD USING THE SAME
    4.
    发明申请
    WIRELESS NETWORK AUDIO SYSTEM HAVING AUTO-PAIRING FUNCTION AND AUTO-PAIRING METHOD USING THE SAME 审中-公开
    具有自动配对功能的无线网络音频系统和使用其的自动配对方法

    公开(公告)号：US20140233755A1

    公开(公告)日：2014-08-21

    申请号：US14097719

    申请日：2013-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-soo KIM ,  Yong-jin KANG ,  Woo-jin HAN ,  Sun-ho YANG

    IPC: H04R3/00

    CPC classification number: H04R3/00 ,  H04L12/2809 ,  H04L2012/2841 ,  H04L2012/2849 ,  H04W4/80 ,  H04W8/005 ,  H04W12/003 ,  H04W12/00504

    Abstract: A system and method of auto-pairing in a wireless network audio system is provided. The auto-pairing method including: entering, by an audio source device, an auto-pairing mode in response to power being supplied; retrieving, by the audio source device, a peripheral wireless speaker; and providing, by the audio source device, a home identifier (ID) for pairing with the wireless speaker in response to the audio source device retrieving the wireless speaker.

    Abstract translation: 提供了一种在无线网络音频系统中自动配对的系统和方法。 所述自动配对方法包括：响应于所提供的电力，由音频源装置输入自动配对模式; 由音频源设备检索外围无线扬声器; 以及响应于所述音频源设备检索所述无线扬声器，由所述音频源设备提供用于与所述无线扬声器配对的归属标识符（ID）。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20180374869A1

    公开(公告)日：2018-12-27

    申请号：US15993756

    申请日：2018-05-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-soo KIM ,  Yong-seok KIM ,  Tae-hun KIM ,  Min-kyung BAE ,  Jae-hoon JANG ,  Kohji KANAMORI

    IPC: H01L27/11582 ,  H01L29/78 ,  H01L29/08

    CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L29/0847 ,  H01L29/7827

    Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200286530A1

    公开(公告)日：2020-09-10

    申请号：US16565579

    申请日：2019-09-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hae-min LEE ,  Kwang-soo KIM ,  Sun-il SHIM

    IPC: G11C5/06 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

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