公开(公告)号：US20230086084A1

公开(公告)日：2023-03-23

申请号：US17554483

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Inchan Hwang ,  Gunho Jo ,  Jeonghyuk Yim ,  Byounghak Hong ,  Kang-ill Seo ,  Ming He ,  JaeHyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

公开(公告)号：US20230178420A1

公开(公告)日：2023-06-08

申请号：US17679465

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  JaeHyun Park ,  Chihak Ahn ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L21/762 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/76283 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/6653

Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

公开(公告)号：US20240047539A1

公开(公告)日：2024-02-08

申请号：US17984025

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  Mehdi Saremi ,  Rebecca Park ,  Muhammed Ahosan Ul Karim ,  Harsono Simka ,  Sungil Park ,  Myungil Kang ,  Kyungho Kim ,  Doyoung Choi ,  JaeHyun Park

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/41791 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/6681 ,  H01L29/8083

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1st polarity type connected to a lower channel structure; an upper source/drain region of a 2nd polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1st region of the 1st polarity type and a 2nd region of the 2nd polarity type.