公开(公告)号：US20180197791A1

公开(公告)日：2018-07-12

申请号：US15914125

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin CHOI ,  Ah-Young CHEON ,  Kwang-Yong YANG ,  Myungil KANG ,  Dohyoung KIM ,  YoonHae KIM

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66545

Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

公开(公告)号：US20220109065A1

公开(公告)日：2022-04-07

申请号：US17550712

申请日：2021-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon LEE ,  Kyungin CHOI ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

公开(公告)号：US20220320278A1

公开(公告)日：2022-10-06

申请号：US17843105

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin CHOI ,  Hyunchul SONG ,  Sunjung KIM ,  Taegon KIM ,  Seong Hoon JEONG

IPC: H01L29/06 ,  H01L29/08 ,  H01L27/092 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/11

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US20160359020A1

公开(公告)日：2016-12-08

申请号：US15131611

申请日：2016-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin CHOI ,  Dongwoo KIM ,  Chang Woo SOHN ,  Youngmoon CHOI

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure extending in a first direction on a substrate, forming a sacrificial gate pattern extending in a second direction to intersect the fin structure, forming a gate spacer layer covering the fin structure and the sacrificial gate pattern, providing a first ion beam having a first incident angle range and a second ion beam having a second incident angle range to the substrate, patterning the gate spacer layer using the first ion beam and the second ion beam to form gate spacers on sidewalls of the sacrificial gate pattern, forming source/drain regions at both sides of the sacrificial gate patterns, and replacing the sacrificial gate pattern with a gate electrode.

Abstract translation: 一种制造半导体器件的方法包括：形成在衬底上沿第一方向延伸的翅片结构，形成沿第二方向延伸以与鳍结构相交的牺牲栅极图案，形成覆盖鳍结构的栅极间隔层和牺牲栅极 提供具有第一入射角范围的第一离子束和具有第二入射角范围的第二离子束到衬底，使用第一离子束和第二离子束来构图栅极间隔层，以在第二离子束的侧壁上形成栅极间隔 牺牲栅极图案，在牺牲栅极图案的两侧形成源极/漏极区域，以及用栅极电极代替牺牲栅极图案。

公开(公告)号：US20220293753A1

公开(公告)日：2022-09-15

申请号：US17491965

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Bae KIM ,  Kyungin CHOI

IPC: H01L29/423 ,  H01L29/417 ,  H01L27/088

Abstract: A semiconductor device is disclosed. The semiconductor device may include a semiconductor substrate including a protruding active pattern, a first gate pattern provided on the active pattern and extended to cross the active pattern, a first capping pattern provided on a top surface of the first gate pattern, the first capping pattern having a top surface, a side surface, and a rounded edge, and a first insulating pattern covering the side surface and the edge of the first capping pattern. A thickness of the first insulating pattern on the edge of the first capping pattern is different from a thickness of the first insulating pattern on outer side surfaces of the spacer patterns.

公开(公告)号：US20220069078A1

公开(公告)日：2022-03-03

申请号：US17242823

申请日：2021-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haejun YU ,  Kyungin CHOI ,  Seung Hun LEE

IPC: H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

公开(公告)号：US20210143271A1

公开(公告)日：2021-05-13

申请号：US16887900

申请日：2020-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon LEE ,  Kyungin CHOI ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

Abstract: An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

公开(公告)号：US20210013306A1

公开(公告)日：2021-01-14

申请号：US17028042

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin CHOI ,  Hyunchul SONG ,  Sunjung KIM ,  Taegon KIM ,  Seong Hoon JEONG

IPC: H01L29/06 ,  H01L29/08 ,  H01L27/092 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/11

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US20240304666A1

公开(公告)日：2024-09-12

申请号：US18667417

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jinbum KIM ,  Gyeom KIM ,  Hyojin KIM ,  Haejun YU ,  Seunghun LEE ,  Kyungin CHOI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.

公开(公告)号：US20230387307A1

公开(公告)日：2023-11-30

申请号：US18360457

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon LEE ,  Kyungin CHOI ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/0649

Abstract: An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.