公开(公告)号：US20210013306A1

公开(公告)日：2021-01-14

申请号：US17028042

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin CHOI ,  Hyunchul SONG ,  Sunjung KIM ,  Taegon KIM ,  Seong Hoon JEONG

IPC: H01L29/06 ,  H01L29/08 ,  H01L27/092 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/11

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US20170358680A1

公开(公告)日：2017-12-14

申请号：US15420512

申请日：2017-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Hoon JEONG ,  Hong Bum PARK ,  HanMei CHOI ,  Jae Young PARK ,  Seung Hyun LIM

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7854 ,  H01L21/28158 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.

公开(公告)号：US20180261677A1

公开(公告)日：2018-09-13

申请号：US15653588

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hoon LEE ,  Hyeon Jin KIM ,  Hoon Joo NA ,  Sung In SUH ,  Chan Hyeong LEE ,  Hu Yong LEE ,  Seong Hoon JEONG ,  Sang Jin HYUN

IPC: H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L21/28

Abstract: A semiconductor device includes a gate insulating layer disposed on a substrate, a first work function tuning layer disposed on the gate insulating layer, a lower barrier conductive layer on and in contact with the first work function tuning layer, and an upper barrier conductive layer on and in contact with the lower barrier conductive layer. The upper barrier conductive layer and the lower barrier conductive layer include a material in common, e.g., they may each include a titanium nitride (TiN) layer.

公开(公告)号：US20160124866A1

公开(公告)日：2016-05-05

申请号：US14715683

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Hoon JEONG ,  Woong SEO ,  Sang Heon LEE ,  Sun Min KWON ,  Ho Young KIM ,  Hee Jun SHIM

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/0207 ,  G06F12/0607 ,  G06F12/0846 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/455

Abstract: A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.

Abstract translation: 提供了缓存存储器及其管理方法。 管理高速缓冲存储器的方法包括：确定存储在存储体中的数据带宽的位的数量是要存储的数据中的单位数据的位数的整数倍，存储第一单位数据 响应于不是单位数据的位数的整数倍的数据带宽的比特数，存储在存储体中的第一地址的第一区域中，并存储部分第二单位数据 被存储在第一地址的第二区域中。

公开(公告)号：US20220320278A1

公开(公告)日：2022-10-06

申请号：US17843105

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin CHOI ,  Hyunchul SONG ,  Sunjung KIM ,  Taegon KIM ,  Seong Hoon JEONG

IPC: H01L29/06 ,  H01L29/08 ,  H01L27/092 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/11

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US20160110889A1

公开(公告)日：2016-04-21

申请号：US14815077

申请日：2015-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Jun SHIM ,  Soo Jung RYU ,  Sang Heon LEE ,  Sun Min KWON ,  Ho Young KIM ,  Seong Hoon JEONG

IPC: G06T11/00

CPC classification number: G06T11/001

Abstract: Provided is a method of processing a texture. The method includes acquiring texture position information in a texture image corresponding to pixel position information of pixels constituting a frame, acquiring texture classification information (TCI) representing a similarity between respective texture factors of two or more classified regions in the texture image based on the texture position information, determining an amount of texture data requested from a memory according to the TCI, and reading texture data corresponding to the determined amount of texture data based on the texture position information.

Abstract translation: 提供了一种处理纹理的方法。 该方法包括：在与构成帧的像素的像素位置信息对应的纹理图像中获取纹理位置信息，基于纹理获取表示纹理图像中两个或更多个分类区域的各个纹理因子之间的相似度的纹理分类信息（TCI） 位置信息，根据TCI确定从存储器请求的纹理数据的量，以及基于纹理位置信息读取与确定的纹理数据量相对应的纹理数据。

公开(公告)号：US20190393303A1

公开(公告)日：2019-12-26

申请号：US16243415

申请日：2019-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin CHOI ,  Hyunchul SONG ,  Sunjung KIM ,  Taegon KIM ,  Seong Hoon JEONG

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/08 ,  H01L27/092 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/11

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US20150206956A1

公开(公告)日：2015-07-23

申请号：US14499922

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  JUNGHO YOO ,  BYEONGCHAN LEE ,  Choeun LEE ,  HYUN JUNG LEE ,  Seong Hoon JEONG ,  BONYOUNG KOO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法包括形成从半导体衬底突出的有源图案，形成与有源图案交叉的伪栅极图案，在伪栅极图案的相对的第一和第二侧壁上形成栅极间隔物，将伪栅极图案去除 形成栅极区域，暴露栅极间隔件之间的有源图案的上表面和侧壁，凹陷由栅极区域暴露的有源图案的上表面，以形成通道凹槽区域，在通道凹槽区域中形成通道图案 选择性外延生长（SEG）工艺，以及顺序地形成覆盖栅极区域中的沟道图案的上表面和侧壁的栅极电介质层和栅电极。 沟道图案具有与半导体衬底不同的晶格常数。

公开(公告)号：US20150206955A1

公开(公告)日：2015-07-23

申请号：US14498996

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Seong Hoon JEONG ,  JEON IL LEE ,  SEOKHOON KIM ,  KWAN HEUM LEE ,  Choeun LEE ,  Yu-Jin PYO

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.

Abstract translation: 本发明构思提供制造半导体器件的方法。 该方法包括图案化衬底以形成有源图案，形成与有源图案相交的栅极图案，在栅极图案的侧壁上形成栅极间隔物，形成覆盖栅极图案的上部区域的生长抑制层，以及形成 源极/漏极在栅极图案的相对的第一和第二侧。

公开(公告)号：US20140120685A1

公开(公告)日：2014-05-01

申请号：US13791870

申请日：2013-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong Hoon JEONG ,  Yoongoo KANG ,  Ho-Kyun AN ,  KONGSOO LEE ,  JAEJONG HAN

IPC: H01L45/00

CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device and method of forming a semiconductor device is disclosed. The method includes forming a first ion-implanted layer having an amorphous state in a substrate; forming an impurity region of a first conductive type in the substrate; forming a semiconductor pattern on the substrate; forming a first doped region of the first conductive type in the semiconductor pattern; and forming a second doped region of a second conductive type contrary to the first conductive type in the semiconductor pattern. The first ion-implanted layer is formed by implanting carbons ions or germanium ions in the substrate.

Abstract translation: 公开了一种形成半导体器件的半导体器件和方法。 该方法包括在基板中形成具有非晶状态的第一离子注入层; 在衬底中形成第一导电类型的杂质区; 在所述基板上形成半导体图案; 在半导体图案中形成第一导电类型的第一掺杂区域; 以及形成与所述半导体图案中的所述第一导电类型相反的第二导电类型的第二掺杂区域。 第一离子注入层通过在基底中注入碳离子或锗离子而形成。