公开(公告)号：US20240234250A9

公开(公告)日：2024-07-11

申请号：US18320423

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo KANG ,  Wookyung YOU ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE ,  Junchae LEE

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L27/088 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

公开(公告)号：US20240234253A1

公开(公告)日：2024-07-11

申请号：US18399173

申请日：2023-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wookyung YOU ,  Yeonggil KIM ,  Sangkoo KANG ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L24/05 ,  H01L25/0657 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L2224/0557 ,  H01L2225/06541 ,  H01L2924/13091

Abstract: A semiconductor device includes: a device structure including a first semiconductor substrate and having an active pattern extending in first direction, a conductive through-via electrically connected to a front wiring layer and penetrating through the first semiconductor substrate, wherein the first semiconductor substrate has a non-planarized lower surface in which a peripheral region around the conductive through-via curves downward, a first bonding structure having a planarized insulating layer disposed on the second surface of the first semiconductor substrate and having a planarized upper surface.

公开(公告)号：US20240136254A1

公开(公告)日：2024-04-25

申请号：US18320423

申请日：2023-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo KANG ,  Wookyung YOU ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE ,  Junchae LEE

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L27/088 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.