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    INTEGRATED CIRCUIT DEVICE
    3.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240234250A9

    公开(公告)日：2024-07-11

    申请号：US18320423

    申请日：2023-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangkoo KANG ,  Wookyung YOU ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE ,  Junchae LEE

    IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088

    CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L27/088 ,  H01L29/66439

    Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

    SEMICONDUCTOR DEVICES
    5.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240258204A1

    公开(公告)日：2024-08-01

    申请号：US18486853

    申请日：2023-10-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeonggil KIM ,  Hoonseok SEO ,  Minchul AHN ,  Wookyung YOU ,  Woojin LEE ,  Junghwan CHUN

    IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending in a second direction on the active region; source/drain regions on the active region and adjacent the gate structure; a backside insulating layer on a lower surface of the substrate; a vertical power structure between adjacent source/drain regions, wherein the vertical power structure extends through the substrate and the backside insulating layer and has an exposed lower surface exposed; an interlayer insulating layer on the backside insulating layer; a backside power structure that extends through the interlayer insulating layer and is connected to the vertical power structure; and a first alignment insulating layer between the backside insulating layer and the interlayer insulating layer, wherein the first alignment insulating layer has a first opening exposing the lower surface of the vertical power structure and contacts the backside power structure.

    SEMICONDUCTOR DEVICE WITH FINE METAL LINES FOR BEOL STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE WITH FINE METAL LINES FOR BEOL STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220336352A1

    公开(公告)日：2022-10-20

    申请号：US17354593

    申请日：2021-06-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taeyong BAE ,  Hoonseok SEO

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

    Abstract: Provided is a semiconductor device including a a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1st fine metal lines arranged in a row with a same pitch, each of the plurality of 1st fine metal lines having a same width; and at least one 1st wide metal line formed at a side of the plurality of 1st fine metal lines, the 1st wide metal line having a width greater than the width of the 1st fine metal line, and wherein each of the plurality of 1st fine metal lines includes a material different from a material included in the 1st wide metal line

    INTEGRATED CIRCUIT DEVICE
    8.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240136254A1

    公开(公告)日：2024-04-25

    申请号：US18320423

    申请日：2023-05-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangkoo KANG ,  Wookyung YOU ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE ,  Junchae LEE

    IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088

    CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L27/088 ,  H01L29/66439

    Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

    SEMI-DAMASCENE STRUCTURE WITH DIELECTRIC HARDMASK LAYER
    9.
    发明申请
    SEMI-DAMASCENE STRUCTURE WITH DIELECTRIC HARDMASK LAYER 有权

    公开(公告)号：US20220375785A1

    公开(公告)日：2022-11-24

    申请号：US17390035

    申请日：2021-07-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoonseok SEO ,  Euibok LEE ,  Taeyong BAE

    IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: A a method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the 1st photoresist pattern; removing the 1st photoresist pattern among the 1st photoresist pattern and the 1st hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the 1st trench with a 2nd inter-metal layer.

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