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1.发明申请公开(公告)号：US20200150894A1
公开(公告)日：2020-05-14
申请号：US16532575
申请日：2019-08-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： SANG-KIL LEE , Chang-kyu Seol , Dae-hyun Kim , Jin-min Kim , Hei-seung Kim , Hyun-mog Park , Hyun-sik Park , Hak-yong Lee
Abstract: A storage device including: a memory controller configured to output user data received from outside of the storage device in a write operation mode and receive read data in a read operation mode; and a memory device including a memory cell array and a random input and output (I/O) engine, the random I/O engine configured to encode the user data provided from the memory controller using a random I/O code, in the write operation mode, and to generate the read data by decoding internal read data read by a data I/O circuit from the memory cell array using the random I/O code, in the read operation mode.
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公开(公告)号：US20140145331A1
公开(公告)日：2014-05-29
申请号：US14056839
申请日：2013-10-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： DOO-HEE HWANG , SANG-KIL LEE
IPC: H01L23/498
CPC classification number: H01L25/0652 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/06135 , H01L2224/06136 , H01L2224/06181 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14136 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/1434 , H01L2924/15311 , H01L2224/05552
Abstract: A multi-chip package may include a system on a chip (SOC) and a plurality of memory devices arranged in the same layer on the SOC. Accordingly, as the multi-chip package may not need to use a TSV, so that manufacturing cost of the multi-chip package is reduced. Moreover, a memory bandwidth between the SOC and the first and second memory devices may increase.
Abstract translation: 多芯片封装可以包括芯片上的系统（SOC）和布置在SOC上的同一层中的多个存储器件。 因此，由于多芯片封装可能不需要使用TSV，所以降低了多芯片封装的制造成本。 此外，SOC和第一和第二存储器件之间的存储器带宽可能增加。
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