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    Bus system
    3.
    发明授权
    Bus system 有权

    公开(公告)号：US10769085B2

    公开(公告)日：2020-09-08

    申请号：US15943647

    申请日：2018-04-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joon-Woo Cho ,  Yun Ju Kwon ,  Sang Woo Kim ,  Woo-Jin Kim

    IPC: G06F11/07 ,  G06F13/362 ,  G06F13/16 ,  G06F13/10 ,  G06F11/30

    Abstract: A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command to the slave functional block. The slave functional block includes a first bus protector. The first bus protector receives the first command on behalf of the slave functional block and transmits a dummy signal corresponding to the first command to the master functional block in response to the slave functional block being in a state of not being able to receive the first command or not being able to transmit a response signal corresponding to the first command.

    BUS SYSTEM
    4.
    发明申请
    BUS SYSTEM 审中-公开

    公开(公告)号：US20190102332A1

    公开(公告)日：2019-04-04

    申请号：US15943647

    申请日：2018-04-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joon-Woo Cho ,  Yun Ju Kwon ,  Sang Woo Kim ,  Woo-Jin Kim

    IPC: G06F13/362 ,  G06F13/16 ,  G06F13/10

    Abstract: A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command to the slave functional block. The slave functional block includes a first bus protector. The first bus protector receives the first command on behalf of the slave functional block and transmits a dummy signal corresponding to the first command to the master functional block in response to the slave functional block being in a state of not being able to receive the first command or not being able to transmit a response signal corresponding to the first command.

    Semiconductor device and semiconductor system
    6.
    发明授权
    Semiconductor device and semiconductor system 有权

    公开(公告)号：US10587265B2

    公开(公告)日：2020-03-10

    申请号：US16107424

    申请日：2018-08-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoo Seok Shon ,  Sang Woo Kim ,  Byung Tak Lee ,  Yun Ju Kwon ,  Joon-Woo Cho

    IPC: G06F1/32 ,  H03K19/00 ,  G06F1/06 ,  G06F1/3234 ,  G06F1/3287

    Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a hardware auto clock gating (HWACG) logic configured to provide clock gating of an intellectual property (IP) block; and a memory power controller configured to perform power gating of a memory electrically connected with the IP block, based on the HWACG logic providing the clock gating for the IP block. The HWACG logic includes a first clock source configured to provide a first clock signal; a second clock source configured to receive the first clock signal provided by the first clock source, and provide a second clock signal to the IP block; a first clock control circuit configured to control the first clock source; and a second clock control circuit configured to transmit a clock request to the first clock control circuit, and control the second clock source, based on an operation state of the IP block.

    Semiconductor device and a method of operating the same
    7.
    发明授权
    Semiconductor device and a method of operating the same 有权

    公开(公告)号：US09985610B2

    公开(公告)日：2018-05-29

    申请号：US15414787

    申请日：2017-01-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Woo Kim ,  Suk Nam Kwon ,  Jin Ook Song

    IPC: H03K3/012 ,  H03K3/037

    CPC classification number: H03K3/0375 ,  H03K3/012

    Abstract: A semiconductor device includes a power gating circuit including a synchronous reset flip-flop, a retention circuit including a retention flip-flop, a clock management circuit configured to provide an operation clock to the power gating circuit and the retention circuit, and a power management circuit configured to transmit a power gating control signal to the power gating circuit, the retention circuit, and the clock management circuit. The power gating circuit is activated to signal entry to a power reduction mode. The retention circuit retains states of the semiconductor device. Upon exit from the power reduction mode, the power management circuit is configured to complete a reset operation of the power gating circuit before signaling the retention circuit to cancel a retention state and restore the states of the semiconductor device.

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