公开(公告)号：US20220351772A1

公开(公告)日：2022-11-03

申请号：US17577198

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inhak LEE ,  Sang-Yeop BAECK ,  Younghwan PARK ,  Jaesung CHOI

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

Abstract: Disclosed is a static random access memory (SRAM) device. According to example embodiments of the present disclosure, a control logic of the SRAM device may include a tracking circuit connected with metal lines for tracking the number of columns of a memory cell array and the number of rows of the memory cell array. By the tracking circuit, a length of word lines of the memory cell array and a length of bit lines of the memory cell array may be tracked. The control logic of the SRAM device may generate control pulses optimized for the size of the memory cell array, based on a tracking result(s) of the tracking circuit. Accordingly, a power and a time necessary for a write operation and a read operation may be reduced.

公开(公告)号：US20180294256A1

公开(公告)日：2018-10-11

申请号：US15842995

申请日：2017-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak LEE ,  Sang-Yeop BAECK ,  JaeSeung CHOI ,  Hyunsu CHOI ,  SangShin HAN

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/7848

Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.

公开(公告)号：US20130343135A1

公开(公告)日：2013-12-26

申请号：US13836902

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Sang-Yeop BAECK ,  Jin-Sung KIM ,  Jang-Hwan YOON

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/222 ,  G11C11/419

Abstract: A semiconductor memory device includes at least one memory cell connected to an internal voltage line that receives a cell power supply voltage and a write assist circuit connected to the internal voltage line. The write assist circuit lowers a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and maintains the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal. The second period succeeds the first period.

Abstract translation: 半导体存储器件包括连接到接收单元电源电压的内部电压线和连接到内部电压线的写入辅助电路的至少一个存储器单元。 写入辅助电路在存储器单元的写入操作的第一周期期间将单元电源电压的电平降低到目标电平，并且在写入的第二周期期间将单元电源电压的电平维持在目标电平 基于写辅助控制信号进行操作。 第二个时期成为第一个时期。

公开(公告)号：US20230337443A1

公开(公告)日：2023-10-19

申请号：US18126761

申请日：2023-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Young TANG ,  Tae-Hyung KIM ,  Dae Young MOON ,  Sang-Yeop BAECK ,  Dong-Wook SEO

IPC: H10B80/00 ,  H10B10/00

CPC classification number: H10B80/00 ,  H10B10/18

Abstract: Provided are a three-dimensional (3D) semiconductor integrated circuit and a static random access memory (SRAM) device. The three-dimensional (3D) semiconductor integrated circuit includes: a first die including a power supply circuit a second die including an SRAM with a through-silicon-via (TSV) bundle region; a third die including a processor; and TSVs, each of which is provided on the TSV bundle region and extends from the TSV bundle region to the third die. The SRAM device includes: a bank array with banks, each of which includes sub-bit-cell arrays and a local peripheral circuit region arranged in a cross (+) shape between the sub-bit-cell arrays; and a global peripheral circuit region including a tail peripheral circuit region extending in a first direction and a head peripheral circuit region extending in a second direction, the tail peripheral circuit region and the head peripheral circuit region being arranged in a “T” shape.

公开(公告)号：US20230186982A1

公开(公告)日：2023-06-15

申请号：US18164199

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung Kang ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  G11C7/08 ,  H10B10/00 ,  H01L23/528 ,  H01L27/092

CPC classification number: G11C11/419 ,  G11C7/08 ,  H10B10/12 ,  H10B10/18 ,  H01L23/5286 ,  H01L27/092

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20190385653A1

公开(公告)日：2019-12-19

申请号：US16555455

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Siddharth Gupta ,  ln-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C11/419 ,  G11C5/14

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US20210383861A1

公开(公告)日：2021-12-09

申请号：US17412588

申请日：2021-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung KANG ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20200005860A1

公开(公告)日：2020-01-02

申请号：US16566002

申请日：2019-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung KANG ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20170221554A1

公开(公告)日：2017-08-03

申请号：US15417807

申请日：2017-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung KANG ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.