公开(公告)号：US20200273507A1

公开(公告)日：2020-08-27

申请号：US16871096

申请日：2020-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Sanghune PARK

IPC: G11C7/22 ,  G06F13/16

Abstract: A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.

公开(公告)号：US20220392520A1

公开(公告)日：2022-12-08

申请号：US17569679

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero KIM ,  Kyunghoi KOO ,  Sujeong KIM ,  Juyoung KIM ,  Sanghune PARK ,  Jiyeon PARK ,  Jihun OH ,  Kyoungwon LEE

IPC: G11C11/4096 ,  G11C11/4076

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US20210249064A1

公开(公告)日：2021-08-12

申请号：US17245064

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan SEONG ,  Soomin LEE ,  Sanghune PARK

IPC: G11C11/4076 ,  G06F11/10

Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.

公开(公告)号：US20190214062A1

公开(公告)日：2019-07-11

申请号：US16118863

申请日：2018-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Sanghune PARK

IPC: G11C7/22 ,  G06F13/16

Abstract: A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.

公开(公告)号：US20170222649A1

公开(公告)日：2017-08-03

申请号：US15392554

申请日：2016-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghoi KOO ,  Sanghune PARK ,  Jin-Ho CHOI

IPC: H03K19/0185 ,  G11C7/10

CPC classification number: H03K19/018521 ,  G11C7/10 ,  G11C7/1057 ,  H03K19/0013 ,  H03K19/00361 ,  H03K19/017509 ,  H03K19/017518 ,  H03K19/018528 ,  H03K19/018592 ,  H03K19/17744

Abstract: A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

公开(公告)号：US20160294381A1

公开(公告)日：2016-10-06

申请号：US15048412

申请日：2016-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangjik Kim ,  Sanghune PARK ,  Jaehyun PARK ,  Jongshin SHIN

IPC: H03K17/28 ,  H03K5/1534 ,  H04L7/04 ,  H03K5/08

CPC classification number: H04L7/04 ,  H03K5/08 ,  H03K5/1534 ,  H03K5/22 ,  H03K17/14 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/028

Abstract: Voltage mode drivers and an electronic apparatus having the same are provided. The voltage mode drivers may include a voltage regulator and a ripple compensation unit connected to an output terminal of the voltage regulator and configured to compare a current data bit of a data pattern with a previous data bit of the data pattern in synchronization with a clock signal input into the ripple compensation unit, generate a control signal when the current data bit is equal to the previous data bit, and apply a ground voltage to the output terminal in response to the control signal.

Abstract translation: 提供电压模式驱动器和具有该电压模式驱动器的电子设备。 电压模式驱动器可以包括电压调节器和纹波补偿单元，其连接到电压调节器的输出端，并被配置为与时钟信号同步地将数据模式的当前数据位与数据模式的先前数据位进行比较 输入到纹波补偿单元，当当前数据位等于先前的数据位时产生控制信号，并且响应于控制信号向输出端施加接地电压。