公开(公告)号：US20240332270A1

公开(公告)日：2024-10-03

申请号：US18475863

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjin Baek ,  Kyung Don Mun ,  Ji Hwang Kim ,  Kyoung Lim Suk

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L28/40 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81801

Abstract: The present disclosure relates to semiconductor packages and methods for manufacturing semiconductor packages. An example semiconductor package includes a top die, first and second bottom dies attached on a lower surface of the top die and being apart from each other by a preset distance, and at least one decoupling capacitor connected to the lower surface of the top die between the first bottom die and the second bottom die. The top die, the first bottom die, and the second bottom die are chiplets.

公开(公告)号：US20240120280A1

公开(公告)日：2024-04-11

申请号：US18214341

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Shanghoon Seo ,  Jihwang Kim ,  Sangjin Baek ,  Hyeonjeong Hwang

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L21/561 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/06 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2924/19106

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor device mounted on the first redistribution structure, a molding layer surrounding the first semiconductor device, a second redistribution structure disposed on the molding layer and the first semiconductor device, a plurality of vertical connection conductors vertically extending in the molding layer and electrically connecting the first redistribution pattern to the second redistribution pattern, a second semiconductor device mounted on the second redistribution structure, the second semiconductor device and the first semiconductor device vertically and partially overlapping each other, a heat dissipation pad structure contacting an upper surface of the first semiconductor device, and a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device along a first straight line extending in a horizontal direction that is parallel to the upper surface of the first semiconductor device.

公开(公告)号：US20240332157A1

公开(公告)日：2024-10-03

申请号：US18500098

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjin Baek ,  Kyungdon Mun

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/81385 ,  H01L2224/81455

Abstract: A semiconductor package includes a redistribution structure including an insulating layer. A plurality of redistribution layers are disposed within the insulating layer. A recess extends from an upper surface of the insulating layer and exposes at least a portion of a first uppermost redistribution layer. A first pad structure is disposed on a bottom and an inner wall of the recess. The first pad structure defines a cavity that is open upwardly. A semiconductor chip is disposed on the upper surface of the redistribution structure and includes a connection terminal electrically connected to the plurality of redistribution layers. A connection bump is disposed within the cavity and electrically connects the connection terminal of the semiconductor chip to the first pad structure of the redistribution structure. An encapsulant covers at least a portion of the semiconductor chip.

公开(公告)号：US20240186231A1

公开(公告)日：2024-06-06

申请号：US18520453

申请日：2023-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwang KIM ,  Joonsung KIM ,  Sangjin Baek ,  Kyounglim Suk

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/181

Abstract: A semiconductor package includes a lower redistribution structure. A semiconductor device is disposed on the lower redistribution structure. A lower encapsulant is disposed on the lower redistribution structure and surrounds a side surface of the semiconductor device. An upper composite redistribution structure is disposed on an upper portion of the semiconductor device and includes a primary conductive structure, a secondary conductive structure disposed on the primary conductive structure, connection vias disposed between the primary conductive structure and the secondary conductive structure, and an upper encapsulant disposed between the primary conductive structure and the secondary conductive structure and surrounding the connection vias.