公开(公告)号：US11973042B2

公开(公告)日：2024-04-30

申请号：US17867388

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jingu Kim ,  Shanghoon Seo ,  Sangkyu Lee ,  Jeongho Lee

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/3511

Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post' and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.

公开(公告)号：US11942434B2

公开(公告)日：2024-03-26

申请号：US17731841

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu Lee ,  Jingu Kim ,  Kyungdon Mun ,  Shanghoon Seo ,  Jeongho Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

公开(公告)号：US11094640B2

公开(公告)日：2021-08-17

申请号：US16590960

申请日：2019-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu Lee ,  Shanghoon Seo ,  Jeongho Lee

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522 ,  H01L23/50

Abstract: A package module includes a core structure including a frame having a penetrating portion, an electronic component disposed in the penetrating portion, and an insulating material covering at least a portion of each of the frame and the electronic component and filling at least a portion of the penetrating portion. The core structure further has a recessed portion in which a stopper layer is disposed on a bottom surface of the recessed portion. A semiconductor chip has a connection pad and is disposed in the recessed portion such that an inactive surface faces the stopper layer. An encapsulant covers at least a portion of each of the core structure and the semiconductor chip, and fills at least a portion of the recessed portion. An interconnect structure is disposed on the core structure and an active surface of the semiconductor chip, and includes a redistribution layer.

公开(公告)号：US20200152569A1

公开(公告)日：2020-05-14

申请号：US16580156

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Hoyeon Jo ,  Shanghoon Seo ,  Younggwan Ko ,  Sangkyu Lee

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

Abstract: A fan-out semiconductor package includes a frame having a recess portion, and a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the semiconductor chip being disposed in the recess portion. One or more through-grooves are disposed around the recess portion and each penetrate through at least a portion of the frame to each extend in a respective direction along a respective side surface of the semiconductor chip. A metal layer is disposed on side walls of the one or more through-grooves, and an encapsulant covers at least a portion of each of the frame and the semiconductor chip and fills at least a portion of the recess portion. A connection structure is disposed on the frame and the active surface of the semiconductor chip, and includes a redistribution layer electrically connected to the connection pad.

公开(公告)号：US20240120280A1

公开(公告)日：2024-04-11

申请号：US18214341

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Shanghoon Seo ,  Jihwang Kim ,  Sangjin Baek ,  Hyeonjeong Hwang

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L21/561 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/06 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2924/19106

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor device mounted on the first redistribution structure, a molding layer surrounding the first semiconductor device, a second redistribution structure disposed on the molding layer and the first semiconductor device, a plurality of vertical connection conductors vertically extending in the molding layer and electrically connecting the first redistribution pattern to the second redistribution pattern, a second semiconductor device mounted on the second redistribution structure, the second semiconductor device and the first semiconductor device vertically and partially overlapping each other, a heat dissipation pad structure contacting an upper surface of the first semiconductor device, and a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device along a first straight line extending in a horizontal direction that is parallel to the upper surface of the first semiconductor device.

公开(公告)号：US11417613B2

公开(公告)日：2022-08-16

申请号：US17016123

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jingu Kim ,  Shanghoon Seo ,  Sangkyu Lee ,  Jeongho Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L23/31

Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post’ and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.

公开(公告)号：US11342274B2

公开(公告)日：2022-05-24

申请号：US16990717

申请日：2020-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu Lee ,  Jingu Kim ,  Kyungdon Mun ,  Shanghoon Seo ,  Jeongho Lee

IPC: H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/10

Abstract: A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

公开(公告)号：US20200161248A1

公开(公告)日：2020-05-21

申请号：US16590960

申请日：2019-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkyu Lee ,  Shanghoon Seo ,  Jeongho Lee

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L23/498 ,  H01L23/50 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A package module includes a core structure including a frame having a penetrating portion, an electronic component disposed in the penetrating portion, and an insulating material covering at least a portion of each of the frame and the electronic component and filling at least a portion of the penetrating portion. The core structure further has a recessed portion in which a stopper layer is disposed on a bottom surface of the recessed portion. A semiconductor chip has a connection pad and is disposed in the recessed portion such that an inactive surface faces the stopper layer. An encapsulant covers at least a portion of each of the core structure and the semiconductor chip, and fills at least a portion of the recessed portion. An interconnect structure is disposed on the core structure and an active surface of the semiconductor chip, and includes a redistribution layer.