公开(公告)号：US20170236921A1

公开(公告)日：2017-08-17

申请号：US15390754

申请日：2016-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungseok MIN ,  Seongjin NAM ,  Sughyun SUNG ,  Youngmook OH ,  Migyeong GWON ,  Hyungdong KIM ,  InWon PARK ,  Hyunggoo LEE

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L23/535 ,  H01L29/08 ,  H01L21/683 ,  H01L29/161 ,  H01L29/165 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/6833 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.

公开(公告)号：US20170133263A1

公开(公告)日：2017-05-11

申请号：US15342456

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungseok MIN ,  Moojin KIM ,  Seongjin NAM ,  Sughyun SUNG ,  YoungHoon SONG ,  Youngmook OH

IPC: H01L21/762 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01J2237/3347 ,  H01L21/02118 ,  H01L21/3065 ,  H01L21/31116 ,  H01L27/10879

Abstract: A method of fabricating a semiconductor device may include forming trenches in a substrate to define a fin structure extending in a direction, forming a device isolation layer to fill the trenches, and removing an upper portion of the device isolation layer to expose an upper side surface of the fin structure. The exposing of the upper side surface of the fin structure may include repeatedly performing an etching cycle including a first step and a second step, and an etching rate of the device isolation layer to the fin structure may be higher in the second step than in the first step.