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    Method and apparatus for parallel data interfacing using combined coding and recording medium therefor
    4.
    发明授权
    Method and apparatus for parallel data interfacing using combined coding and recording medium therefor 有权
    用于使用组合编码和记录介质的并行数据接口的方法和装置

    公开(公告)号：US09048855B2

    公开(公告)日：2015-06-02

    申请号：US14047377

    申请日：2013-10-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seung Jun Bae ,  Jong Keun Ahn ,  Kwang Chol Choe

    IPC: H03M5/00 ,  H03K19/003 ,  H04L25/03 ,  H04L25/14 ,  H04L25/49

    CPC classification number: H03M5/00 ,  H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

    Abstract: A semiconductor device may include a coding lookup table unit including a plurality of coding lookup tables each of which is selected by a respectively selection signal, and a selection unit configured to receive one of N-bit parallel data and extract respective encoded data corresponding to the selection signal and to which the N-bit parallel data is mapped from the coding lookup table unit, and encoded data and extract respective N-bit parallel data corresponding to the selection signal and to which the encoded data is mapped from the coding lookup table unit, wherein N is 2 or an integer greater than 2, and wherein the coding lookup tables respectively store a plurality of coded data patterns that respectively correspond to patterns of the N-bit parallel data and are random temporally and spatially.

    Abstract translation: 半导体器件可以包括编码查找表单元，其包括多个编码查找表，每个编码查找表通过分别选择信号选择;以及选择单元，被配置为接收N位并行数据中的一个，并提取对应于 选择信号，并且从编码查找表单元映射N位并行数据，并且对编码数据进行编码，并且从编码查找表单元提取与选择信号相对应的与编码数据对应的N位并行数据， 其中N是2或大于2的整数，并且其中编码查找表分别存储分别对应于N位并行数据的模式并且在时间上和空间上是随机随机的多个编码数据模式。

    Semiconductor memory device with multiple sub-memory cell arrays and memory system including same
    5.
    发明授权
    Semiconductor memory device with multiple sub-memory cell arrays and memory system including same 有权
    具有多个子存储单元阵列的半导体存储器件和包括其的存储器系统

    公开(公告)号：US09384092B2

    公开(公告)日：2016-07-05

    申请号：US14300289

    申请日：2014-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dae Hyun Kim ,  Seung Jun Bae ,  Young Soo Sohn ,  Tae Young Oh ,  Won Jin Lee

    IPC: G11C29/42 ,  G06F11/10 ,  G11C7/08 ,  G11C7/06 ,  G11C29/54 ,  G11C11/4091 ,  G11C11/419

    CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/419

    Abstract: A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

    Abstract translation: 半导体存储器件包括： 存储单元阵列，包括存储具有第一特性的第一数据的第一子存储单元阵列和存储具有与第一特性不同的第二特性的第二数据的第二子存储单元阵列;第一外围电路， 子存储器单元阵列，以执行指向第一子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个，以及仅与第二子存储单元阵列可操作地相关联的第二外围电路， 执行指向第二子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个。

    Semiconductor devices, methods of operating semiconductor devices, and systems having the same
    6.
    发明授权
    Semiconductor devices, methods of operating semiconductor devices, and systems having the same 有权
    半导体器件，半导体器件的操作方法以及具有该半导体器件的系统

    公开(公告)号：US08693603B2

    公开(公告)日：2014-04-08

    申请号：US13668965

    申请日：2012-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin Gook Kim ,  Dae Hyun Chung ,  Seung Jun Bae ,  Seung Hoon Lee ,  Won Hwa Shin

    IPC: H04L12/66

    CPC classification number: H03L7/0812 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107 ,  H04L7/0008 ,  H04L7/0091

    Abstract: A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal as a first input. The phase detector generates a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit. The semiconductor device further includes a data port, a memory core storing data, and a serializer, in response to the timing signal output from the selection circuit, serializing data output from the memory core and outputting serialized data to the controller via the data port. The controller generates the first selection signal based on at least one of the voltage signal and the serialized data.

    Abstract translation: 半导体器件包括选择电路和相位检测器。 选择电路响应于从控制器输出的第一选择信号，作为定时信号输出从控制器输出的第一时钟信号或使用第一时钟信号作为第一输入的PLL的输出信号。 相位检测器产生指示从控制器输出的第二时钟信号与从选择电路输出的定时信号之间的相位差的电压信号。 半导体器件还包括数据端口，存储数据存储器核心和串行器，响应于从选择电路输出的定时信号，串行化从存储器核心输出的数据并经由数据端口将串行数据输出到控制器。 控制器基于电压信号和序列化数据中的至少一个产生第一选择信号。

    SEMICONDUCTOR DEVICES, METHODS OF OPERATING SEMICONDUCTOR DEVICES, AND SYSTEMS HAVING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICES, METHODS OF OPERATING SEMICONDUCTOR DEVICES, AND SYSTEMS HAVING THE SAME 有权
    半导体器件，操作半导体器件的方法及其相关系统

    公开(公告)号：US20130064030A1

    公开(公告)日：2013-03-14

    申请号：US13668965

    申请日：2012-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin Gook Kim ,  Dae Hyun Chung ,  Seung Jun Bae ,  Seung-hoon Lee ,  Won Hwa Shin

    IPC: G11C8/18 ,  G11C7/00

    CPC classification number: H03L7/0812 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107 ,  H04L7/0008 ,  H04L7/0091

    Abstract: A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal as a first input. The phase detector generates a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit. The semiconductor device further includes a data port, a memory core storing data, and a serializer, in response to the timing signal output from the selection circuit, serializing data output from the memory core and outputting serialized data to the controller via the data port. The controller generates the first selection signal based on at least one of the voltage signal and the serialized data.

    Abstract translation: 半导体器件包括选择电路和相位检测器。 选择电路响应于从控制器输出的第一选择信号，作为定时信号输出从控制器输出的第一时钟信号或使用第一时钟信号作为第一输入的PLL的输出信号。 相位检测器产生指示从控制器输出的第二时钟信号与从选择电路输出的定时信号之间的相位差的电压信号。 半导体器件还包括数据端口，存储数据存储器核心和串行器，响应于从选择电路输出的定时信号，串行化从存储器核心输出的数据并经由数据端口将串行数据输出到控制器。 控制器基于电压信号和序列化数据中的至少一个产生第一选择信号。

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