公开(公告)号：US20220328454A1

公开(公告)日：2022-10-13

申请号：US17853140

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee JANG ,  Kyung Suk OH ,  Eunseok SONG ,  Seung-Yong CHA

IPC: H01L25/065 ,  H01L25/18

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

公开(公告)号：US20210118848A1

公开(公告)日：2021-04-22

申请号：US16883153

申请日：2020-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee JANG ,  Kyung Suk OH ,  Eunseok SONG ,  Seung-Yong CHA

IPC: H01L25/065 ,  H01L25/18

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

公开(公告)号：US20160172291A1

公开(公告)日：2016-06-16

申请号：US14957053

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsuk KIM ,  HyunJong MOON ,  Tai-Hyun EUM ,  Heeseok LEE ,  Keung Beum KIM ,  Yonghoon KIM ,  Yoonha JUNG ,  Seung-Yong CHA

IPC: H01L23/498 ,  H01L23/34

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block.

Abstract translation: 半导体封装可以包括具有顶表面和与顶表面相对的底表面的封装衬底，封装衬底的顶表面被配置为具有安装在其上的半导体芯片，封装衬底中的功率块和接地块， 所述功率块被配置为穿过所述封装衬底的电力通路，并且所述接地块被配置为穿过所述封装衬底的接地路径，从所述功率块和所述接地块延伸的第一通孔以及电连接到所述半导体芯片的所述第一通孔， 第二通孔从功率块和接地块延伸到封装衬底的底表面，并且阻挡通孔以穿透功率块和接地块，块通孔电连接到半导体芯片并与功率块电分离， 地块。

公开(公告)号：US20160133542A1

公开(公告)日：2016-05-12

申请号：US14825831

申请日：2015-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yong CHA ,  Keung Beum KIM ,  Yonghoon KIM ,  HyunJong MOON ,  Heeseok LEE

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/16265 ,  H01L2224/1713 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041

Abstract: A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

Abstract translation: 半导体封装包括：封装基板，包括第一区域，穿透第一区域并在封装基板的顶表面和底表面处露出的热块;封装基板上的半导体芯片;设置在封装基板和半导体芯片之间的凸块;以及 包括与热块接触的第一凸起，以及设置在封装基板的底表面上并包括与热块接触的第一端子的端子。 热块是功率路径和接地路径之一。