公开(公告)号：US20030036239A1

公开(公告)日：2003-02-20

申请号：US10034043

申请日：2001-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-soon Lim ,  Seung-hwan Lee ,  Han-mei Choi ,  Yun-jung Lee ,  Gab-jin Nam ,  Ki-yeon Park ,  Young-sun Kim ,  Sung-tae Kim

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/8242 ,  H01L021/20

CPC classification number: H01L28/55

Abstract: A method for manufacturing a capacitor of a semiconductor device is provided. The method includes the steps of: forming a first electrode on a semiconductor substrate; forming a dielectric layer on the first electrode; forming a second electrode on the dielectric layer; first annealing the capacitor having the first electrode, the dielectric layer, and the second electrode under oxygen atmosphere; and second annealing the capacitor having the first electrode, the dielectric layer, and the second electrode under vacuum.

Abstract translation: 提供一种用于制造半导体器件的电容器的方法。 该方法包括以下步骤：在半导体衬底上形成第一电极; 在所述第一电极上形成介电层; 在所述电介质层上形成第二电极; 在氧气氛下首先退火具有第一电极，电介质层和第二电极的电容器; 以及在真空下对具有第一电极，电介质层和第二电极的电容器进行第二次退火。

公开(公告)号：US20040227164A1

公开(公告)日：2004-11-18

申请号：US10823420

申请日：2004-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC: H01L029/74

CPC classification number: H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

Abstract translation: 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US20040192001A1

公开(公告)日：2004-09-30

申请号：US10795175

申请日：2004-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

IPC: H01L021/331

CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/7375 ,  H01L29/7378

Abstract: A method of manufacturing a bipolar device including pre-treatment using germane gas and a bipolar device manufactured by the same. The method includes forming a single crystalline silicon layer for a base region on a collector region; and forming a polysilicon layer for an emitter region thereon. Here, before the polysilicon layer is formed, the single crystalline silicon layer is pre-treated using germane gas. Thus, an oxide layer is removed from the single crystalline silicon layer, and a germanium layer is formed on the single crystalline silicon layer, thus preventing Si-rearrangement.

Abstract translation: 一种制造双极器件的方法，其包括使用锗烷气体的预处理和由其制造的双极器件。 该方法包括在集电区上形成用于基区的单晶硅层; 并在其上形成发射极区的多晶硅层。 这里，在形成多晶硅层之前，使用锗烷气预处理单晶硅层。 因此，从单晶硅层去除氧化物层，并且在单晶硅层上形成锗层，从而防止Si重排。

公开(公告)号：US20040002862A1

公开(公告)日：2004-01-01

申请号：US10452431

申请日：2003-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-ho Kim ,  Hyun-woo Park ,  Tae-su Kim ,  Mi-jung Noh ,  Byung-ho Min ,  Ki-won Jo ,  Sung-hwan Jo ,  Seung-hwan Lee ,  Jin-won Jeong ,  Ho-rang Jang ,  Sun-hee Park ,  Keun-cheol Hong ,  Sung-jae Kim

IPC: G10L015/00

CPC classification number: G10L15/02 ,  G10L15/142 ,  G10L19/0212 ,  G10L2015/025

Abstract: A voice recognition device including dedicated arithmetic calculating modules for arithmetic operations that are more frequently required among arithmetic operations necessary for voice recognition, an observation probability calculating device for calculating probabilities that each of the phonemes of a pre-selected word can be observed upon voice recognition, a complex Fast Fourier Transform (FFT) calculation device and method of calculating a complex FFT of complex data, a cache, and a cache controlling method are provided. The arithmetic modules interpret commands received from a receiver and perform operations indicated by the commands.

Abstract translation: 一种语音识别装置，包括用于语音识别所需的算术运算中更经常需要的用于算术运算的专用算术运算模块，用于计算在语音识别后可以观察到预选词的每个音素的概率的观测概率计算装置 提供了复数快速傅里叶变换（FFT）计算装置和计算复数数据的复数FFT，高速缓存和高速缓存控制方法的方法。 算术模块解释从接收器接收的命令，并执行命令所指示的操作。

公开(公告)号：US20030060042A1

公开(公告)日：2003-03-27

申请号：US10127651

申请日：2002-04-22

Applicant: Samsung Electronics Co. Ltd.

Inventor： Hee-sook Park ,  Gil-heyun Choi ,  Seung-hwan Lee ,  Yun-jung Lee

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/44

CPC classification number: H01L21/76843 ,  H01L21/28562 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/75 ,  H01L28/90

Abstract: A method for fabricating a semiconductor device is provided. A ruthenium layer is formed on a semiconductor substrate in a processing chamber. A barrier layer is formed on the ruthenium layer supplying a halide-free precursor in the processing chamber. A metal layer such as an aluminum layer, an aluminum alloy layer, a tungsten layer, or a copper layer is formed on the barrier layer. The barrier layer is one of a TiN layer, a TaN layer, a WN layer, and an MoN layer. The TiN layer is one of formed by using an MOCVD process and an ALD process, and the halide-free precursor is a titanium compound selected from the group consisting of pentakis(diethylamino) titanium, tetrakis(diethylamino) titanium, tetrakis(dimethylamino) titanium, and pentakis(dimethylamino) titanium. The TaN layer is formed by using one of an MOCVD process and an ALD process, and the halide-free precursor is a tantalum compound selected from the group consisting of t-butyltrikis(diethylamino) tantalum, pentakis(diethylamino) tantalum, tetrakis(dimethylamino) tantalum, and pentakis(dimethylamino) tantalum.

Abstract translation: 提供一种制造半导体器件的方法。 在处理室中的半导体衬底上形成钌层。 在处理室中提供无卤素前体的钌层上形成阻挡层。 在阻挡层上形成铝层，铝合金层，钨层，铜层等金属层。 阻挡层是TiN层，TaN层，WN层和MoN层之一。 TiN层是通过使用MOCVD法和ALD法形成的，并且不含卤化物的前体是选自五（二乙基氨基）钛，四（二乙基氨基）钛，四（二甲基氨基）钛，四 ，和五（二甲基氨基）钛。 通过使用MOCVD法和ALD法之一形成TaN层，无卤素前体是选自叔丁基（二乙氨基）钽，五（二乙基氨基）钽，四（二甲基氨基） ）钽和五（二甲基氨基）钽。