公开(公告)号：US20240363633A1

公开(公告)日：2024-10-31

申请号：US18470684

申请日：2023-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG YANG ,  Seungchan YUN ,  Sooyoung Park ,  Jaehong Lee ,  KANG-ILL SEO

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H03K17/687

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor on a substrate. The transistor may include: a pair of thin semiconductor layers spaced apart from each other; a channel region between the pair of thin semiconductor layers; a gate electrode on the pair of thin semiconductor layers and the channel region; and a gate insulator separating the gate electrode from both the pair of thin semiconductor layers and the channel region. A side surface of the channel region may be recessed with respect to side surfaces of the pair of thin semiconductor layers and may define a recess between the pair of thin semiconductor layers. A portion of the gate insulator and/or a portion of the gate electrode may be in the recess.

公开(公告)号：US20230101171A1

公开(公告)日：2023-03-30

申请号：US17536939

申请日：2021-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seungchan YUN ,  Kang-ill SEO

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

公开(公告)号：US20250031444A1

公开(公告)日：2025-01-23

申请号：US18380476

申请日：2023-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Jaejik Baek ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a three-dimension (3D) stacked semiconductor device which includes: a 1stsource/drain region connected to a 1st channel structure; and a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure, wherein the 2nd channel structure has a smaller length than the 1st channel structure in a channel-length direction, in which the 2nd source/drain region is connected to a 3rd source/drain region through the 2nd channel structure.

公开(公告)号：US20240395900A1

公开(公告)日：2024-11-28

申请号：US18380951

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Jason MARTINEAU ,  Kang-ill SEO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes: a 1st source/drain region; a 2nd source/drain region; a channel structure connecting the 1st source/drain region to the 2nd source/drain region; a gate structure configured to control the channel structure; a backside source/drain contact structure connected to a bottom surface of the 1st source/drain region; a backside isolation structure at a lower portion of the semiconductor device; and a 1st contact spacer on the backside source/drain contact structure, wherein the 1st contact spacer is configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure.

公开(公告)号：US20240290689A1

公开(公告)日：2024-08-29

申请号：US18215985

申请日：2023-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Wonhyuk Hong ,  Keumseok Park ,  Se Jung Park ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including: a channel structure; source/drain regions connected by the channel structure; and a backside contact structure formed below at least one of the source/drain region, wherein, in a 1st-direction cross section view, a width of an upper portion of the backside contact structure close to the source/drain region is smaller than a width of a lower portion of the backside contact structure distant from the source/drain region, wherein, in a 2nd-direction cross-section view, widths of the upper portion and the lower portion of the backside contact structure are substantially uniform along a vertical downward direction, and wherein the 1st direction intersects the 2nd direction.

公开(公告)号：US20240162309A1

公开(公告)日：2024-05-16

申请号：US18135530

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung YANG ,  Myunghoon JUNG ,  Seungmin SONG ,  Seungchan YUN ,  Sejung PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/8221 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is a three-dimensional field-effect transistor (3DSFET) device including: a 1st source/drain region on a substrate, and a 2nd source/drain region on the 1st source/drain region; and a 1st source/drain contact structure on the 1st source/drain region, and a 2nd source/drain contact structure on the 2nd source/drain region, wherein the 2nd source/drain region is isolated from the 1st source/drain region through an interlayer structure, and wherein a spacer is formed at an upper portion of a sidewall of the 2nd source/drain contact structure, between the 1st source/drain contact structure and the 2nd source/drain contact structure.

公开(公告)号：US20230343845A1

公开(公告)日：2023-10-26

申请号：US17891777

申请日：2022-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Gunho JO ,  Seungchan YUN ,  Jaejik BAEK

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/78696 ,  H01L29/41775 ,  H01L29/0673 ,  H01L21/823412 ,  H01L21/823437

Abstract: Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.

公开(公告)号：US20230343824A1

公开(公告)日：2023-10-26

申请号：US17964677

申请日：2022-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Jaejik Baek ,  Gunho Jo ,  Byounghak Hong ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L25/11 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L25/117 ,  H01L29/78696 ,  H01L21/823412 ,  H01L29/78672

Abstract: Provided is a multi-stack semiconductor device that includes: a substrate; a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower work-function metal layer and a lower gate electrode; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper work-function metal layer and an upper gate electrode, wherein each of the lower gate electrode and the upper gate electrode includes a metal or a metal compound, and wherein the lower gate electrode comprises polycrystalline silicon (poly-Si) or poly-Si comprising a dopant, and the upper gate electrode comprises a metal or a metal compound.

公开(公告)号：US20250120183A1

公开(公告)日：2025-04-10

申请号：US18954980

申请日：2024-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myunghoon JUNG ,  Jaehong LEE ,  Seungchan YUN ,  Kang-ill SEO

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate structure.

公开(公告)号：US20250098324A1

公开(公告)日：2025-03-20

申请号：US18586112

申请日：2024-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Myunghoon Jung ,  Kang-ill Seo

IPC: H01L27/06 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device which includes: 1st source/drain regions connected through a 1st channel structure which is controlled by a 1st gate structure; and a 2nd source/drain regions, respectively above the 1st source/drain regions, connected through a 2nd channel structure which is controlled by a 2nd gate structure, wherein the 1st channel structure and the 2nd channel structure comprise different materials.