公开(公告)号：US11183527B2

公开(公告)日：2021-11-23

申请号：US16410386

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang Zhang ,  Shi Li Quan ,  Hyung-yong Kim ,  Seug-gab Park ,  In-gyu Baek ,  Kyung-rae Byun ,  Jin-yong Choi

IPC: H01L27/146 ,  H04N5/335

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

公开(公告)号：US20150249130A1

公开(公告)日：2015-09-03

申请号：US14713349

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong JEONG ,  Jeong-Yun Lee ,  Shi Li Quan ,  Dong-Suk Shin ,  Si-Hyung Lee

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7851

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.

公开(公告)号：US11508775B2

公开(公告)日：2022-11-22

申请号：US17398493

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang Zhang ,  Shi Li Quan ,  Hyung-yong Kim ,  Seug-gab Park ,  In-gyu Baek ,  Kyung-rae Byun ,  Jin-yong Choi

IPC: H01L27/146 ,  H04N5/335

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

公开(公告)号：US09318575B2

公开(公告)日：2016-04-19

申请号：US14313039

申请日：2014-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Li Quan

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes forming a gate structure including a polysilicon gate and forming a capping spacer on a side surface of the gate structure to prevent parasitic epitaxial growth on the side surface of the polysilicon gate.

Abstract translation: 一种形成半导体器件的方法包括在栅极结构的侧表面上形成包括多晶硅栅极并形成封盖间隔物的栅极结构，以防止多晶硅栅极的侧表面上的寄生外延生长。

公开(公告)号：US09263521B2

公开(公告)日：2016-02-16

申请号：US14713349

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Li Quan ,  Dong-Suk Shin ,  Si-Hyung Lee

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7851

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.

公开(公告)号：US20150126012A1

公开(公告)日：2015-05-07

申请号：US14313039

申请日：2014-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Li Quan

IPC: H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes forming a gate structure including a polysilicon gate and forming a capping spacer on a side surface of the gate structure to prevent parasitic epitaxial growth on the side surface of the polysilicon gate.

Abstract translation: 一种形成半导体器件的方法包括在栅极结构的侧表面上形成包括多晶硅栅极并形成封盖间隔物的栅极结构，以防止多晶硅栅极的侧表面上的寄生外延生长。